Synchronizing the operation of multiple equilizers in a digital
communications system
    1.
    发明授权
    Synchronizing the operation of multiple equilizers in a digital communications system 失效
    在数字通信系统中同步多个均衡器的操作

    公开(公告)号:US5163066A

    公开(公告)日:1992-11-10

    申请号:US705246

    申请日:1991-05-24

    IPC分类号: H04L7/02 H04L25/03 H04L25/14

    摘要: In a dual-duplex system wherein the communications channels have associated propagation delays which are typically different from one another, equalizers are connected to operate upon the signal received from each channel. To synchronize the operation of these equalizers to each other, the coefficients of each equalizer are updated when the training sequence is received from at least one of the communications channels. The sequence of symbol values in the training sequence may either be known or unknown to the receiver prior to transmission. When this sequence is detected, the coefficient updating circuit for each equalizer operates in response to a common reference signal. This reference signal includes a plurality of symbols and the value of each symbol is supplied at the same time to each equalizer coefficient updating circuit. This technique generates coefficients which compensate for propagation delay differences between the communications channels and is applicable to communications systems wherein data is distributed and transmitted through a plurality of communications channels.

    摘要翻译: 在双工双工系统中,其中通信信道具有通常彼此不同的相关联的传播延迟,均衡器被连接以对从每个信道接收到的信号进行操作。 为了使这些均衡器的操作彼此同步,当从至少一个通信信道接收到训练序列时,更新每个均衡器的系数。 在发送之前,训练序列中的符号值的序列可以是接收器的已知或未知的。 当检测到该序列时,每个均衡器的系数更新电路响应于公共参考信号而工作。 该参考信号包括多个符号,并且每个符号的值同时被提供给每个均衡器系数更新电路。 该技术产生补偿通信信道之间的传播延迟差异的系数,并且可应用于通过多个通信信道分发和发送数据的通信系统。

    Digital signal processor architecture
    2.
    发明授权
    Digital signal processor architecture 失效
    数字信号处理器架构

    公开(公告)号:US4843581A

    公开(公告)日:1989-06-27

    申请号:US48189

    申请日:1987-05-11

    IPC分类号: H03H17/06

    CPC分类号: H03H17/06 H03H2218/08

    摘要: The computational processing power of a Digital Signal Processor (DSP) in linear-phase Finite Impulse Response Filter (FIR) applications is essentially doubled by taking advantage of either the even (symmetrical) or odd (antisymmetrical) symmetry of the response of such a filter.

    摘要翻译: 通过利用这种滤波器的响应的均匀(对称)或奇数(反对称)对称性,线性相有限脉冲响应滤波器(FIR)应用中的数字信号处理器(DSP)的计算处理能力基本上是双倍的 。

    Equalizer-based timing recovery
    3.
    发明授权
    Equalizer-based timing recovery 失效
    基于均衡器的定时恢复

    公开(公告)号:US4815103A

    公开(公告)日:1989-03-21

    申请号:US113973

    申请日:1987-10-29

    IPC分类号: H04L7/02 H04L25/03 H04B3/04

    CPC分类号: H04L7/0058 H04L25/03044

    摘要: In a data receiver employing a fractionally spaced equalizer, the phase with which samples of the received signal are formed is controlled in response to a signal indicative of the center of gravity of the equalizer coefficient.

    摘要翻译: 在采用分数间隔均衡器的数据接收机中,响应于指示均衡器系数的重心的信号来控制形成接收信号的采样的相位。

    Equalizer-based timing recovery
    4.
    发明授权
    Equalizer-based timing recovery 失效
    基于均衡器的定时恢复

    公开(公告)号:US5353312A

    公开(公告)日:1994-10-04

    申请号:US815010

    申请日:1991-12-27

    IPC分类号: H03H21/00 H04L7/02 H03H7/30

    摘要: Timing recovery circuitry for recovering digital data generates a timing signal which is a function of the delay provided by an equalizer to one or more predetermined frequency components of its input signal. Advantageously, this approach is applicable to systems which utilize one or more baseband or passband equalizers. The disclosed embodiments of the present invention pertain to a dual-duplex system. In such a system, the digital data to be transmitted is divided into two different digital signals and each signal is coupled through an associated transmission channel. At the receiver, the received version of each transmitted signal is processed by an associated equalizer and the outputs therefrom are combined to recover the digital data. In the disclosed embodiments of the present invention, the necessary timing signal for such recovery is a function of the delay introduced by each equalizer to at least one predetermined frequency component of that equalizer's input signal.

    摘要翻译: 用于恢复数字数据的定时恢复电路产生定时信号,其是由均衡器提供给其输入信号的一个或多个预定频率分量的延迟的函数。 有利地,该方法适用于利用一个或多个基带或通带均衡器的系统。 所公开的本发明的实施例涉及双工双工系统。 在这样的系统中,要发送的数字数据被分成两个不同的数字信号,并且每个信号通过相关联的传输信道耦合。 在接收机处,每个发射信号的接收版本由相关联的均衡器处理,并且其输出被组合以恢复数字数据。 在本发明的所公开的实施例中,用于这种恢复的必要的定时信号是由均衡器与该均衡器的输入信号的至少一个预定频率分量引入的延迟的函数。

    Frequency dependent I/Q imbalance compensation
    5.
    发明授权
    Frequency dependent I/Q imbalance compensation 有权
    频率依赖I / Q不平衡补偿

    公开(公告)号:US09020026B2

    公开(公告)日:2015-04-28

    申请号:US12985564

    申请日:2011-01-06

    申请人: Robert L. Cupo

    发明人: Robert L. Cupo

    CPC分类号: H04B1/30 H04L27/3863

    摘要: A method and system for compensating for frequency dependent phase and amplitude imbalances is provided. A plurality of frequency sub-bands is extracted from a received wideband signal. Each of the plurality of frequency sub-bands is compensated to produce an associated plurality of compensated frequency sub-bands. The compensated sub-bands are summed in order to produce a compensated signal.

    摘要翻译: 提供了一种用于补偿频率相关相位和幅度不平衡的方法和系统。 从接收的宽带信号中提取多个频率子带。 多个频率子带中的每一个被补偿以产生相关联的多个补偿的频率子带。 补偿的子带被相加以产生补偿信号。

    Frequency Dependent I/Q Imbalance Compensation
    7.
    发明申请
    Frequency Dependent I/Q Imbalance Compensation 有权
    频率依赖I / Q不平衡补偿

    公开(公告)号:US20120177084A1

    公开(公告)日:2012-07-12

    申请号:US12985564

    申请日:2011-01-06

    申请人: Robert L. Cupo

    发明人: Robert L. Cupo

    IPC分类号: H04B1/00

    CPC分类号: H04B1/30 H04L27/3863

    摘要: A method and system for compensating for frequency dependent phase and amplitude imbalances is provided. A plurality of frequency sub-bands is extracted from a received wideband signal. Each of the plurality of frequency sub-bands is compensated to produce an associated plurality of compensated frequency sub-bands. The compensated sub-bands are summed in order to produce a compensated signal.

    摘要翻译: 提供了一种用于补偿频率相关相位和幅度不平衡的方法和系统。 从接收的宽带信号中提取多个频率子带。 多个频率子带中的每一个被补偿以产生相关联的多个补偿的频率子带。 将补偿的子带相加以产生补偿信号。

    Phase jitter correction arrangement
    8.
    发明授权
    Phase jitter correction arrangement 失效
    相位抖动校正装置

    公开(公告)号:US5115452A

    公开(公告)日:1992-05-19

    申请号:US562050

    申请日:1990-08-02

    申请人: Robert L. Cupo

    发明人: Robert L. Cupo

    IPC分类号: H04L27/38 H04L1/20 H04L27/22

    CPC分类号: H04L1/205

    摘要: In a communications system, a transmitted signal is typically impaired by phase jitter attributed to power line harmonics and ringing voltages present in a communications channel. In order to properly recover the transmitted signal, the phase jitter in a received signal needs to be eliminated. To this end, an infinite-impulse-response (IIR) filter arrangement is employed in a receiver to estimate the phase jitter and is followed by a demodulator which substantially removes the jitter based on the estimate. The transfer function of this IIR filter arrangement is a function of the autocorrelation of a phase error, the latter being indicative of the difference between the phase jitter in the received signal and the jitter estimate.

    摘要翻译: 在通信系统中,发送信号通常受到归因于通信信道中存在的电力线谐波和振铃电压的相位抖动的损害。 为了适当地恢复发送的信号,需要消除接收信号中的相位抖动。 为此,在接收机中采用无限脉冲响应(IIR)滤波器布置来估计相位抖动,并且其后面是基于估计基本上消除抖动的解调器。 该IIR滤波器装置的传递函数是相位误差的自相关函数的函数,后者表示接收信号中的相位抖动与抖动估计之间的差异。

    Phase jitter compensation arrangement using an adaptive IIR filter
    9.
    发明授权
    Phase jitter compensation arrangement using an adaptive IIR filter 失效
    使用自适应IIR滤波器的相位抖动补偿布置

    公开(公告)号:US4847864A

    公开(公告)日:1989-07-11

    申请号:US209801

    申请日:1988-06-22

    申请人: Robert L. Cupo

    发明人: Robert L. Cupo

    CPC分类号: H04L27/01

    摘要: A voice-band data symbol is typically impaired by so-called phase jitter prior to symbol being received at a data modem. Modem circuitry estimates the phase angle of the jitter and an infinite-impulse-response (IIR) filter adjusts to that phase angle so that the jitter can be corrected for by a demodulator circuit. Advantageously, the IIR filter is arranged so that its pair of complex, conjugate poles are initially positioned at a first predetermined radius within a unit circle. The angular displacement of the poles around the unit circle is adaptively increased in response to receipt of a series of such estimates until such displacement substantially equals the phase angle of the jitter. The poles are then positioned at a second predetermined radius to increase the gain of the filter.