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    Non-volatile memory with predictive programming
    1.
    发明授权
    Non-volatile memory with predictive programming 有权
    具有预测编程的非易失性存储器

    公开(公告)号：US08243520B2

    公开(公告)日：2012-08-14

    申请号：US12610781

    申请日：2009-11-02

    申请人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

    发明人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

    IPC分类号： G11C11/34

    CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/06

    摘要： A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

    摘要翻译： 操作集成电路的方法包括将至少一个第一编程脉冲施加到多个非易失性存储器单元以调整每个非易失性存储单元的存储参数的电平，所述至少一个第一编程脉冲被定义 通过多个具有固定值的脉冲参数，并且通过测量具有超过验证电平的存储参数电平的多个非易失性存储器单元的非易失性存储器单元的数量来确定故障计数。 该方法还包括基于故障计数确定多个非易失性存储器单元的编程行为的变化，将由多个脉冲参数定义的至少一个第二编程脉冲的至少一个脉冲参数的值调整为 基于编程行为的变化的期望值，以及将所述至少一个第二编程脉冲应用于所述多个非易失性存储器单元。

    NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING
    2.
    发明申请
    NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING 有权
    具有预测编程的非易失性存储器

    公开(公告)号：US20110103150A1

    公开(公告)日：2011-05-05

    申请号：US12610781

    申请日：2009-11-02

    申请人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

    发明人： Nigel Chan ,  Wolf Allers ,  Michael Bollu ,  Dimitri Lebedev ,  Jan Otterstedt ,  Christian Peters

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/06

    摘要： A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

    摘要翻译： 操作集成电路的方法包括将至少一个第一编程脉冲施加到多个非易失性存储器单元以调整每个非易失性存储单元的存储参数的电平，所述至少一个第一编程脉冲被定义 通过多个具有固定值的脉冲参数，并且通过测量具有超过验证电平的存储参数电平的多个非易失性存储器单元的非易失性存储器单元的数量来确定故障计数。 该方法还包括基于故障计数确定多个非易失性存储器单元的编程行为的变化，将由多个脉冲参数定义的至少一个第二编程脉冲的至少一个脉冲参数的值调整为 基于编程行为的变化的期望值，以及将所述至少一个第二编程脉冲应用于所述多个非易失性存储器单元。

    Data retention monitor
    4.
    发明授权
    Data retention monitor 有权
    数据保留监视器

    公开(公告)号：US07864565B2

    公开(公告)日：2011-01-04

    申请号：US11831448

    申请日：2007-07-31

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016

    摘要： A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

    摘要翻译： 一种用于包括电压源和电压比较器的存储单元的数据保持监视器。 电压源适于向存储器单元提供可选择的电压。 可选择的电压包括读取电压和测试电压，测试电压大于读取电压。 电压比较器适于在将存储单元提供可选择的电压之后将存储单元的电压与参考电压进行比较。 当至少部分由测试电压产生的存储单元电压基本上等于参考电压时，存储单元保留数据。

    DATA RETENTION MONITOR
    6.
    发明申请
    DATA RETENTION MONITOR 有权
    数据保持监控

    公开(公告)号：US20090034343A1

    公开(公告)日：2009-02-05

    申请号：US11831448

    申请日：2007-07-31

    申请人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Thomas Nirschl ,  Jan Otterstedt ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3431 ,  G11C16/349 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016

    摘要： A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

    摘要翻译： 一种用于包括电压源和电压比较器的存储单元的数据保持监视器。 电压源适于向存储器单元提供可选择的电压。 可选择的电压包括读取电压和测试电压，测试电压大于读取电压。 电压比较器适于在将存储单元提供可选择的电压之后将存储单元的电压与参考电压进行比较。 当至少部分由测试电压产生的存储单元电压基本上等于参考电压时，存储单元保留数据。

    Method of operating phase-change memory
    7.
    发明授权
    Method of operating phase-change memory 有权
    操作相变存储器的方法

    公开(公告)号：US08670270B2

    公开(公告)日：2014-03-11

    申请号：US13402895

    申请日：2012-02-23

    申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

    摘要： One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

    摘要翻译： 一个或多个实施例可以涉及一种操作相变存储器元件的方法，包括：提供所述相变存储元件，所述相变存储元件具有第一端子和第二端子; 引起从第一端子到第二端子的存储元件的第一电流; 并且引起从第二端到第一端的存储元件的第二电流，其中使第一电流将存储器元件从第一电阻状态编程到第二电阻状态，并且使得第二电流从存储元件 第一电阻状态到第二电阻状态。

    METHOD OF OPERATING PHASE-CHANGE MEMORY
    8.
    发明申请
    METHOD OF OPERATING PHASE-CHANGE MEMORY 有权
    操作相变记忆的方法

    公开(公告)号：US20130058159A1

    公开(公告)日：2013-03-07

    申请号：US13402895

    申请日：2012-02-23

    申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

    摘要： One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

    摘要翻译： 一个或多个实施例可以涉及一种操作相变存储器元件的方法，包括：提供所述相变存储元件，所述相变存储元件具有第一端子和第二端子; 引起从第一端子到第二端子的存储元件的第一电流; 并且引起从第二端到第一端的存储元件的第二电流，其中使第一电流将存储器元件从第一电阻状态编程到第二电阻状态，并且使得第二电流从存储元件 第一电阻状态到第二电阻状态。

    Differential sensing method and system for STT MRAM
    9.
    发明授权
    Differential sensing method and system for STT MRAM 有权
    STT MRAM差分感测方法及系统

    公开(公告)号：US08837210B2

    公开(公告)日：2014-09-16

    申请号：US13592404

    申请日：2012-08-23

    申请人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    发明人： Mihail Jefremow ,  Wolf Allers ,  Jan Otterstedt ,  Christian Peters ,  Thomas Kern

    IPC分类号： G11C11/00

    CPC分类号： G11C29/028 ,  G11C11/16 ,  G11C11/1673 ,  G11C29/021 ,  G11C2029/5006

    摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.

    摘要翻译： 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 根据本发明的一个方面，用于读取存储单元的系统包括读取通道和预充电路径。 参考电流通过读取路径提供，并通过读取路径中的采样元件进行采样。 随后，通过相同的采样元件和读取路径提供来自存储单元的电流。 然后，输出电平由针对采样参考电流工作的电池电流确定。