SYSTEM TO VERIFY MARKETABLE TITLE OF REAL ESTATE AND RELATED METHODS

    公开(公告)号:US20180101918A1

    公开(公告)日:2018-04-12

    申请号:US15729997

    申请日:2017-10-11

    Applicant: Robert PALMER

    Inventor: Robert PALMER

    CPC classification number: G06Q50/16 G06F16/95 G06Q30/018 H04L67/02

    Abstract: A system to verify marketable title of real estate includes a graphical user interface (“GUI”) installed on a remote computer and configured for a user to transmit a request for a title defect indicator search for a selected piece of real estate. The system also includes a transmission server in electronic communication with a data source and the remote computer, and configured to receive the request for the title defect indicator search. The transmission server includes a microprocessor that is configured generate and transmit a title defect alert for a selected piece of real estate that includes a title defect indicator rating to the remote computer. In addition, the microprocessor is further configured to retrieve owner information of the piece of real estate from the data source, and transmit the owner information to a broker computer not associated with the user.

    SYSTEM TO MARKET REAL ESTATE AND RELATED METHODS

    公开(公告)号:US20180189904A1

    公开(公告)日:2018-07-05

    申请号:US15862034

    申请日:2018-01-04

    Applicant: Robert PALMER

    Inventor: Robert PALMER

    CPC classification number: G06Q50/16 A47G1/0638 G09F1/10 G09F5/02 G09F7/00

    Abstract: A method to market real estate includes providing a graphical user interface to a user for installation on a remote computer, receiving a street address at a server for a particular piece of real estate from the remote computer, and receiving digital photographs at the server of the particular piece of real estate. The server includes a microprocessor and a memory that stores user preferences for a marketing format and the street address, where the microprocessor formats the digital photographs in accordance with the user preferences and the marketing format, and generates a plurality of physical marketing items for the particular piece of real estate in accordance with the user preferences. The plurality of physical marketing items includes at least one of a door hangtag, a postcard, a thank you card, and a sign. The method also includes assembling the plurality of physical marketing items into a display box.

    REDUNDANCY FOR ON-CHIP INTERCONNECT
    3.
    发明申请
    REDUNDANCY FOR ON-CHIP INTERCONNECT 有权
    用于片上互连的冗余

    公开(公告)号:US20140075403A1

    公开(公告)日:2014-03-13

    申请号:US13612629

    申请日:2012-09-12

    CPC classification number: G06F17/5031

    Abstract: One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

    Abstract translation: 一个实施例提出了片上源同步,基于CMOS中继器的互连的片上满足定时要求的技术。 片上互连的每个通道可以包括一个或多个冗余电线。 校准逻辑被配置为将转换模式应用于包括每个通道的线和响应于捕获转换模式而生成的校准图案。 基于校准模式,选择最能满足片上互连的时序要求的导线用于传输数据。 校准逻辑还基于捕获的校准模式修整时钟和所选数据线的延迟,以提高片上互连的时序裕度。 提高片上互连的时序裕度提高了芯片产量。

    SYSTEM TO GENERATE REAL ESTATE LEADS AND RELATED METHODS

    公开(公告)号:US20180189905A1

    公开(公告)日:2018-07-05

    申请号:US15862048

    申请日:2018-01-04

    Applicant: Robert PALMER

    Inventor: Robert PALMER

    CPC classification number: G06Q50/16 B42D15/02 G06Q30/0257 G06Q30/0267

    Abstract: A method to generate real estate leads includes publishing a plurality of marketing items for a real estate listing with a telephone number and a unique code printed thereon. The unique code is configured to be transmitted by a mobile communication device and the unique code printed on each piece of the plurality of marketing items is different. The method also includes sending the plurality of marketing items to a plurality of street addresses, where the unique code is assigned to a particular street address of the plurality of street addresses. In addition, the method includes receiving a communication from the mobile communication device at the remote device associated with the telephone number, where the communication includes the unique code, and in response to receiving the unique code, determining the particular street address assigned to the unique code and creating a file that stores data of the communication.

    SYSTEM TO MONITOR AND PROVIDE ALERTS AFFECTING TITLE OF REAL ESTATE

    公开(公告)号:US20180189903A1

    公开(公告)日:2018-07-05

    申请号:US15861991

    申请日:2018-01-04

    Applicant: Robert PALMER

    Inventor: Robert PALMER

    Abstract: A system to monitor and provide alerts of events affecting title of real estate includes a remote computer of a user, a GUI installed on the remote computer of the user, a data source, and a transmission server configured to receive title event data from the data source over a communications network pursuant to a transmission schedule. The transmission server includes a microprocessor configured to filter the received title event data for title event data for the selected piece of real estate, generate a title event alert from the filtered data that contains the identity of the selected piece of real estate and a description of the filtered title event data for the selected piece of real estate, format the title event alert into data blocks according to the information format, and transmit the formatted title event alert over the communications network to the remote computer.

    TIMING CALIBRATION FOR ON-CHIP INTERCONNECT
    6.
    发明申请
    TIMING CALIBRATION FOR ON-CHIP INTERCONNECT 有权
    片上互连的时序校准

    公开(公告)号:US20140070862A1

    公开(公告)日:2014-03-13

    申请号:US13612614

    申请日:2012-09-12

    CPC classification number: H03K5/131 H01L2924/0002 H03K5/133 H01L2924/00

    Abstract: One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.

    Abstract translation: 一个实施例提出了用于片上源同步,互补金属氧化物半导体(CMOS)基于中继器的互连的定时校准技术。 可以应用两个转换模式来校准片上数据或时钟线的延迟。 校准逻辑被配置为应用转换模式,然后基于捕获的校准模式修剪时钟和数据线的延迟。 微调使用可配置的延迟电路来调整时钟和数据线的延迟。 定时误差可能由串扰,电源引起的抖动(PSIJ)或由于晶体管和导线金属化不匹配引起的导线延迟变化引起。 可以通过减少由于片上互连的不同导线之间的不匹配延迟引起的定时误差的出现来提高芯片产量。

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