公开(公告)号：US4786827A

公开(公告)日：1988-11-22

申请号：US879160

申请日：1986-06-26

申请人： Roberto Gariboldi ,  Marco Morelli

发明人： Roberto Gariboldi ,  Marco Morelli

IPC分类号： H01L27/082 ,  G05F1/56 ,  G05F1/569 ,  H01L21/8222 ,  H03K17/0422 ,  H03K3/33 ,  G05F1/40 ,  H03K3/01

CPC分类号： H03K17/0422 ,  G05F1/569

摘要： Described is an antisaturation circuit for an integrated PNP transistor characterized by a comparator circuit comprising two transistors and a current generator whose output current corresponds to a pre-established function, e.g., an exponential function, of the emitter current of said transistor. The changing of state of the comparator circuit, as determined by said pre-established function of said current generator, is determined by the drop of the V.sub.CE voltage of the transistor below a preset minimum value, with a portion of the conduction current of one of the two transistors of the comparator circuit utilized for increasing the forced .beta. of the transistor. This limits the degree of its saturation, as well as the leakage current toward the substrate.

摘要翻译： 描述了用于集成PNP晶体管的抗饱和电路，其特征在于包括两个晶体管的比较器电路和电流发生器，其输出电流对应于所述晶体管的发射极电流的预先建立的功能，例如指数函数。 由所述电流发生器的所述预先建立的功能确定的比较器电路的状态的改变由晶体管的VCE电压降到预定的最小值以下，其中导电电流的一部分为 比较器电路的两个晶体管用于增加晶体管的强制β。 这限制了其饱和度以及朝向衬底的漏电流。

公开(公告)号：US5874850A

公开(公告)日：1999-02-23

申请号：US919592

申请日：1997-08-05

申请人： Francesco Pulvirenti ,  Roberto Gariboldi

发明人： Francesco Pulvirenti ,  Roberto Gariboldi

IPC分类号： H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073 ,  H02M3/07

摘要： A charge pump MOS voltage booster has reduced voltage drops and ripple. This voltage booster is advantageously used in two applications. The voltage has four MOS transistors instead of diodes in a classical voltage booster, which exhibit an undesired voltage drop. The voltage booster also has an oscillator with two outputs and two corresponding charge transfer capacitors. In this manner, the undesired voltage drops and ripple are reduced without complicating the circuitry structure.

摘要翻译： 电荷泵MOS升压器降低了电压降和纹波。 该升压器有利地用于两个应用中。 电压具有四个MOS晶体管，而不是典型的升压器中的二极管，其表现出不期望的电压降。 升压器还具有带两个输出的振荡器和两个相应的电荷转移电容器。 以这种方式，不需要电压降和纹波减小而不使电路结构复杂化。

公开(公告)号：US4899098A

公开(公告)日：1990-02-06

申请号：US211925

申请日：1988-06-27

申请人： Roberto Gariboldi

发明人： Roberto Gariboldi

IPC分类号： G05F1/569

CPC分类号： G05F1/569

摘要： A series voltage regulator includes a protective circuit that detects the collector current from a PBP power transistor and the collector-emitter voltage thereof. Such current and voltage signals are generated, respectively, by an auxiliary PNP transistor having a collector current which is proportional to that of the PNP power transistor, and by a circuit connected between the emitter and the collector of the PNP power transistor. The collector current and collector emitter voltage signals are processed by a circuit which, whenever the current and voltage values are greater than preset maximum values, reduces the PNP power transistor current and maintains it within permissible limits. The protective circuit does not affect the minimum voltage drop between the input and output of the regulator and may be dimensioned so as to use the maximum extent of the S.O.A. of the PNP power transistor.

摘要翻译： 串联稳压器包括检测来自PBP功率晶体管的集电极电流及其集电极 - 发射极电压的保护电路。 这样的电流和电压信号分别由具有与PNP功率晶体管的集电极电流成比例的集电极电流以及连接在PNP功率晶体管的发射极和集电极之间的电路的辅助PNP晶体管产生。 集电极电流和集电极发射极电压信号由电路进行处理，每当电流和电压值大于预设的最大值时，电路会降低PNP功率晶体管电流并将其保持在允许的极限内。 保护电路不影响调节器的输入和输出之间的最小电压降，并且其尺寸可以使用S.O.A.的最大范围。 的PNP功率晶体管。

公开(公告)号：US20050057466A1

公开(公告)日：2005-03-17

申请号：US10897381

申请日：2004-07-22

申请人： Leonardo Sala ,  Daniele Domanin ,  Roberto Gariboldi

发明人： Leonardo Sala ,  Daniele Domanin ,  Roberto Gariboldi

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3622 ,  G09G3/2014 ,  G09G3/2025 ,  G09G3/2077 ,  G09G2330/021

摘要： A method for driving low consumption LCD modules, the LCD modules having a multiplicity of display elements located at the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes, the method includes the phases of applying an M bit electrical digital signal to at least one row electrode at a time, subdivided in a plurality of time intervals equal to 2M−1, the electrical digital signal suitable for illuminating each of the display elements with a predefined luminosity level chosen from among 2M luminosity levels, each of the M bits is applied for a preset duration, then reducing the preset duration of each of the M bits in accordance with a predefined scale factor K and subdividing the M bits in (2M−1)/K plurality of time intervals.

摘要翻译： 一种用于驱动低消耗LCD模块的方法，所述LCD模块具有位于具有多个行电极和多个列电极的矩阵的交点处的多个显示元件，所述方法包括施加M位电数字 信号到至少一个行电极，被细分为等于2-M的多个时间间隔，该电数字信号适于用从2M中选择的预定亮度级别照亮每个显示元件 >亮度级别，每个M比特被施加预设的持续时间，然后根据预定义的比例因子K减少每个M比特的预设持续时间，并将M比特细分为（2-M -1）/ K多个时间间隔。

公开(公告)号：US5747978A

公开(公告)日：1998-05-05

申请号：US622459

申请日：1996-03-22

申请人： Roberto Gariboldi ,  Francesco Pulvirenti

发明人： Roberto Gariboldi ,  Francesco Pulvirenti

IPC分类号： G01R19/165 ,  G05F1/46 ,  G05F3/26 ,  G05F3/28 ,  G05F3/30 ,  G11C5/14 ,  H02J1/00 ,  G05F3/16

CPC分类号： G11C5/147 ,  G05F1/465 ,  G05F3/267

摘要： A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator having an input terminal and an output terminal, and a voltage divider connected between a first supply voltage reference and a second voltage reference and connected to the input terminal of the comparator, further provides for the output terminal of said comparator to be connected to the input terminal through at least one feedback network comprising at least one current generator. The feedback network further comprises a buffer block having an input terminal connected to said comparator and a first output terminal connected to a switch which is connected between a circuit node of said voltage divider and the second voltage reference.

摘要翻译： 一种用于产生参考电压并检测电源电压下降的电路，包括至少一个具有输入端和输出端的阈值比较器，以及分压器，连接在第一电源电压基准和第二电压基准之间，并连接到 比较器的输入端还通过包括至少一个电流发生器的至少一个反馈网络提供所述比较器的输出端子连接到输入端子。 反馈网络还包括缓冲块，其具有连接到所述比较器的输入端子和连接到开关的第一输出端子，该开关连接在所述分压器的电路节点和第二参考电压之间。

公开(公告)号：US5453678A

公开(公告)日：1995-09-26

申请号：US83721

申请日：1993-06-24

申请人： Luca Bertolini ,  Roberto Gariboldi

发明人： Luca Bertolini ,  Roberto Gariboldi

IPC分类号： G05F1/56 ,  G05F1/46 ,  G06K7/00 ,  H02H1/04

CPC分类号： H02H1/043 ,  G05F1/468 ,  G06K7/0008

摘要： A regulator including a power element between the input terminal and output terminal; and a regulating loop including a differential stage for comparing the output voltage of the regulator with a reference voltage and accordingly driving a gain stage connected to the power element. The output voltage is picked up by the differential stage via a resistive divider, the resistance of which varies according to the value of a logic signal at a control input. When the resistance of the divider changes, the inputs of the differential stage are so unbalanced as to produce an output voltage up or down ramp equal to the slew rate of the regulating loop and proportional to the bias current of the differential stage. Over the up ramp, the shorting protection circuit is turned off for a predetermined time .tau., whereas, over the down ramp, a stage is turned on for absorbing the discharge current of the capacitive load.

摘要翻译： 一种调节器，包括输入端子和输出端子之间的功率元件; 以及调节回路，其包括用于将调节器的输出电压与参考电压进行比较的差分级，并因此驱动连接到功率元件的增益级。 输出电压由差分级通过电阻分压器拾取，电阻分压器根据控制输入端的逻辑信号值而变化。 当分压器的电阻变化时，差分级的输入是不平衡的，以产生输出电压上升或下降斜坡等于调节回路的转换速率并与差动级的偏置电流成正比。 在上升斜坡上，短路保护电路关闭预定时间τ，而在下降斜坡上，一个阶段被接通以吸收容性负载的放电电流。

公开(公告)号：US4882532A

公开(公告)日：1989-11-21

申请号：US254763

申请日：1988-10-07

申请人： Roberto Gariboldi ,  Alberto Gola

发明人： Roberto Gariboldi ,  Alberto Gola

IPC分类号： G05F3/16 ,  G05F1/10 ,  G05F1/56 ,  H01H47/22 ,  H02H9/04 ,  H03K17/082 ,  H03K17/16 ,  H03K17/64

CPC分类号： H03K17/0826 ,  H01H47/22 ,  H02H9/047

摘要： A circuit for limiting the transient overvoltage across a power transistor connected in series with an inductive load between a supply rail and a ground rail of the circuit and operated to switch ON-OFF the inductive load utilizes a comparator circuit for switching-ON again the power transistor in order to discharge the energy stored in the load's inductance. The voltage across the power transistor is sensed by a first voltage divider, while a reference voltage is obtained by a second voltage divider connected between the supply and ground. The circuit is practically insensitive to temperature and to variations of the supply voltage and is easily implemented.

公开(公告)号：US06507227B2

公开(公告)日：2003-01-14

申请号：US09948144

申请日：2001-09-06

申请人： Angelo Genova ,  Roberto Gariboldi ,  Aldo Novelli ,  Giulio Ricotti

发明人： Angelo Genova ,  Roberto Gariboldi ,  Aldo Novelli ,  Giulio Ricotti

IPC分类号： H03K301

CPC分类号： G01R19/16519 ,  H02M2001/0009

摘要： The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

公开(公告)号：US6031412A

公开(公告)日：2000-02-29

申请号：US96401

申请日：1998-06-11

申请人： Angelo Genova ,  Mario Tarantola ,  Giuseppe Cantone ,  Roberto Gariboldi

发明人： Angelo Genova ,  Mario Tarantola ,  Giuseppe Cantone ,  Roberto Gariboldi

IPC分类号： H03K17/06 ,  G05F1/10

CPC分类号： H03K17/063 ,  H03K2217/0018

摘要： A circuit for charging a capacitance using an LDMOS integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance. The circuit avoids the switch-on of parasitic bipolar transistors of the LDMOS structure during transient states. The circuit includes a number of junctions directly biased between a source node and a body node of the LDMOS transistor, a current generator referred to a ground of the circuit, at least one switch between the source and a first junction of a chain of directly biased junctions, and a limiting resistor connected between the body and the current generator referred to ground. The switch is open during a charging phase of the capacitance and is closed when the charging voltage of the capacitance exceeds a preestablished threshold responsive to a control signal. The switch is controlled by a logic signal active during the phase in which the supply voltage of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging the body with a current whose maximum value is limited to a preestablished value.

摘要翻译： 使用以模拟电容的高压充电二极管的方式控制的LDMOS集成晶体管对电容进行充电的电路。 该电路避免了在瞬态状态期间LDMOS结构的寄生双极晶体管的接通。 电路包括直接偏置在LDMOS晶体管的源极节点和体节点之间的多个结，称为电路接地的电流发生器，源极和直接偏置的链的第一结之间的至少一个开关 接头和连接在主体和电流发生器之间的限制电阻器是指地面。 开关在电容的充电阶段打开，并且当电容的充电电压响应于控制信号超过预先建立的阈值时闭合。 开关由在集成电路的电源电压低于同一集成电路的最小接通电压的相位中的逻辑信号控制，用于对电池充电，其电流的最大值被限制为 预先确定的价值。

公开(公告)号：US5710690A

公开(公告)日：1998-01-20

申请号：US488885

申请日：1995-06-09

申请人： Gregorio Bontempo ,  Francesco Pulvirenti ,  Paolo Colletti ,  Roberto Gariboldi

发明人： Gregorio Bontempo ,  Francesco Pulvirenti ,  Paolo Colletti ,  Roberto Gariboldi

IPC分类号： H02H3/08 ,  H03K17/082 ,  H03K17/284 ,  H02H3/18

CPC分类号： H03K17/284 ,  H03K17/0822

摘要： A non-dissipative device for protecting an integrated circuit having multiple independent channels against overloading. The non-dissipative device includes an input terminal and an output terminal having an integrated switch connected therebetween which consists of an input portion, a logic gate with two inputs a control portion, and an output portion, all connected in series with one another. The device further includes a generating circuit for generating the on-times and off-times of the integrated switch, the generating circuit is connected between an output of the output portion and an input of the logic gate.

摘要翻译： 一种用于保护具有多个独立通道的集成电路以防超载的非耗散装置。 非耗散装置包括输入端子和输出端子，其具有连接在其间的集成开关，其由输入部分，具有两个输入的控制部分的逻辑门和输出部分组成，所述输出部分彼此串联连接。 该装置还包括用于产生集成开关的导通和关断时间的发生电路，该发生电路连接在输出部分的输出端和逻辑门的输入端之间。