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1.发明授权Network switch including hysteresis in signalling fullness of transmit queues 有权网络交换机包括发送队列信令充满时的滞后公开(公告)号：US06762995B1
公开(公告)日：2004-07-13
申请号：US09593506
申请日：2000-06-14
IPC分类号： H04L1256
CPC分类号： H04L47/10 , H04L47/29 , H04L47/30 , H04L49/103 , H04L49/254 , H04L49/30 , H04L49/3018 , H04L49/3027 , H04L49/351
摘要： A multiport network device includes a multiplicity of receive queues, a multiplicity of transmit queues and a forwarding engine for transferring entries from the receive queues to the transmit queues. When a transmit queue is greater than a first hysteresis point, the forwarding engine prevents transfer of entries from a receive queue to the transmit queue and transfer of entries to the transmit queue is allowed when the length of the transmit queue falls below a second hysteresis point.
摘要翻译： 多端口网络设备包括多个接收队列，多个发送队列和用于将条目从接收队列传送到发送队列的转发引擎。 当发送队列大于第一滞后点时，转发引擎防止将条目从接收队列传送到发送队列，并且当发送队列的长度落在第二滞后点以下时允许传送到发送队列的条目 。
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公开(公告)号：US06975627B1
公开(公告)日：2005-12-13
申请号：US09417102
申请日：1999-10-13
CPC分类号： H04L12/4666 , H04L29/06 , H04L69/22
摘要： An Ethernet data packet including a VLAN tag header and a VLAN identification field is modified. The modification is accomplished by inserting in place of the VLAN tag header a field of the same size including selected information. The VLAN identification may be retained. The inserted field may include a first field indicating the presence of the VLAN identification field and a second field of selected information, the second field being longer than the first field.
摘要翻译： 修改包含VLAN标签头和VLAN标识字段的以太网数据包。 通过将VLAN标签头替换为包含所选信息的相同大小的字段来实现修改。 可以保留VLAN标识。 所插入的字段可以包括指示VLAN识别字段的存在的第一字段和所选信息的第二字段，第二字段长于第一字段。
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公开(公告)号：US06594270B1
公开(公告)日：2003-07-15
申请号：US09353148
申请日：1999-07-14
IPC分类号： H04L1266
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals. The system thereby defines ageing by means of pointers and avoids the ambiguities or inconvenience of known recycling ageing schemes.
摘要翻译： 一种分组存储器系统，包括具有用于存储数据分组的多个可寻址存储器位置的存储器空间，指针控制装置，用于生成逐渐定义将数据写入存储器空间的写指针，以及逐渐定义的读指针 其中要从存储器空间读取数据和定义一连串间隔的老化时钟。 指针控制装置产生一个“当前”指针和一个“丢弃”指针，并且对于每个间隔，操作使“当前”指针对应于写指针的紧前一个值，并使丢弃指针对应于 以这种方式，“丢弃”指针和读取指针之间的存储器空间的部分表示在所述存储器空间中对于所述间隔中的至少两个的数据。 因此，该系统通过指针来定义老化，并避免已知的再循环老化方案的模糊或不方便。
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4.发明授权Inhibition of underrun in network switches and the like for packet-based communication systems 失效对于基于分组的通信系统，在网络交换机等中抑制欠载公开(公告)号：US06611520B1
公开(公告)日：2003-08-26
申请号：US09386482
申请日：1999-08-31
IPC分类号： H04L1256
CPC分类号： H04L49/901 , H04L47/6215 , H04L49/103 , H04L49/205 , H04L49/351 , H04L49/55 , H04L49/90 , H04L49/9031 , H04L49/9036 , H04L49/9057
摘要： A multi-port data communication device includes a common central memory through which all data packets must pass. Packet data is written to and read from the common memory space in bursts in response to receive write requests and transmit read requests. A transmit read request for a first burst of data in a packet has in a central arbiter a relatively low priority and transmit read requests for a second and any subsequent burst of data in a packet have in the central arbiter a relatively high priority. Preferably the receive write requests have in said central arbiter a priority intermediate said relatively low priority and said relatively high priority. The priority system reduces the likelihood of underrun and overrun particularly when the burst size is generally smaller than the packet size.
摘要翻译： 多端口数据通信设备包括所有数据分组必须通过的公共中央存储器。 响应于接收写入请求并发送读取请求，分组数据以脉冲串的形式写入公共存储器空间并从其读取。 分组中的第一数据突发的发送读请求在中央仲裁器中具有相对较低的优先级，并且对分组中的第二和任何后续数据突发的发送读请求在中央仲裁器中具有相对高的优先级。 优选地，所述接收写入请求在所述中央仲裁器中具有所述相对较低优先级和所述相对较高优先级的优先级。 优先级系统降低了运行和超限的可能性，特别是当突发大小通常小于分组大小时。
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5.发明授权Network switch including restriction of source address look-ups based on receive queue length 失效网络交换机包括基于接收队列长度限制源地址查找公开(公告)号：US06683875B1
公开(公告)日：2004-01-27
申请号：US09564792
申请日：2000-05-05
IPC分类号： H04L1256
CPC分类号： H04L49/351 , H04L49/201 , H04L49/30
摘要： A network switch which can perform in respect of addressed data packets source address and destination address look-ups in a forwarding database includes a control which inhibits the performance of source address look-ups if the length of a respective receive queue of packets is greater than a threshold. The inhibition may endure until the length of the receive queue falls below a second threshold lower than the first. The inhibition may not be applied if the respective receive queue is subject to head of line blocking
摘要翻译： 可以对转发数据库中的寻址数据分组源地址和目的地址查找执行的网络交换机包括如果分组的相应接收队列的长度大于的话，则禁止源地址查找的性能的控制 一个门槛。 抑制可以持续到接收队列的长度低于低于第一阈值的第二阈值。 如果相应的接收队列受到线路阻塞的影响，则禁止可能不被应用
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公开(公告)号：US06265930B1
公开(公告)日：2001-07-24
申请号：US09562953
申请日：2000-05-03
IPC分类号： H03K1762
CPC分类号： H04L7/0083 , G06F1/08 , H03L7/00 , H04J3/0688
摘要： A clock selector circuit for selecting a single output clock signal from a multiplicity of input clock signals, each constituted by transitions between binary states, comprises a multiplicity of D-bistables each having a clock input coupled to receive the respective one of the input clock signals, a D-input coupled to receive a hold signal common to the bistables, and an output for providing a respective hold signal. A first multiplexer has inputs coupled to receive the respective input clock signals and is operative to select in response to the selection signal one of said input signals. A second multiplexer has inputs coupled to receive the respective hold signals and is operative to select in response to the selection signal the hold signal corresponding to the clock signal selected by the first multiplexer. A gate is coupled to receive both the clock signal selected by the first multiplexer and the hold signal selected by the second multiplexer and asserts an output whichever of the input signals to the gate may be asserted. The assertion of the common hold signal precedes a chance in state of the selection signal and endures at least until all the hold signals have been asserted and a change in state of the selection signal has occurred. The circuit facilitates glitch-free clock multiplexing.
摘要翻译： 一种用于从多个输入时钟信号中选择单个输出时钟信号的时钟选择器电路，每个输入时钟信号由二进制状态之间的转换构成，包括多个D双稳态电路，每个具有时钟输入端耦合以接收相应的一个输入时钟信号 ，耦合以接收双绞线共用的保持信号的D输入端和用于提供相应保持信号的输出端。 第一多路复用器具有耦合以接收相应输入时钟信号的输入，并且可操作以响应于选择信号选择所述输入信号之一。 第二复用器具有耦合以接收相应保持信号的输入，并且可操作以响应于选择信号来选择与由第一多路复用器选择的时钟信号对应的保持信号。 门被耦合以接收由第一多路复用器选择的时钟信号和由第二多路复用器选择的保持信号，并且断言输出到门的输入信号中的哪一个可以被断言。 公共保持信号的断言先于选择信号状态的机会，并且至少持续至所有保持信号已被确认并且选择信号的状态发生变化。 该电路有助于无毛刺时钟复用。
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公开(公告)号：US06293706B1
公开(公告)日：2001-09-25
申请号：US09511113
申请日：2000-02-23
申请人： Richard JA Strike , Justin A Drummond-Murray , Christopher Byham , Malcolm G Brown , Lee C Harrison
发明人： Richard JA Strike , Justin A Drummond-Murray , Christopher Byham , Malcolm G Brown , Lee C Harrison
IPC分类号： G02B636
CPC分类号： G02B6/3817 , G02B6/3893 , G02B6/3895 , G02B6/4292
摘要： A socket connector has a single socket including fiber optic terminals 10 and wire terminals 12 and is adapted to receive alternatively in respectively inverted positions either a first plug connector for cooperation with the fiber optic terminals or a second plug connector for cooperation with the wire terminals, in each case without engagement with the terminals with which the plug should not cooperate. The connector includes respective latching slots 7 and 11 in opposite walls 5 and 3 for the respective plug connectors.
摘要翻译： 插座连接器具有包括光纤端子10和电线端子12的单个插座，并且适于在分别倒置的位置中交替地接收用于与光纤端子配合的第一插头连接器或用于与线端子配合的第二插头连接器， 在每种情况下，不与插头不能配合的端子接合。 连接器包括在相应的插头连接器的相对壁5和3中的相应的锁定槽7和11。
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公开(公告)号：US06795946B1
公开(公告)日：2004-09-21
申请号：US09565481
申请日：2000-05-05
IPC分类号： H03M1300
CPC分类号： H04L1/00
摘要： Apparatus for performing a cyclic redundancy code check on a binary digital signal consisting of a variable multiplicity (M) of data bytes comprises a buffer register for temporarily storing in succession segments each consisting of an integral number (N) of bytes. Each successive segment is loaded into a cyclic redundancy checker which produces a remainder after performing polynomial division of the digital signal. When the number of bytes of the digital signal in the last segment is less than the integral plurality (N) that last segment is padded with constant data. The signal is deemed valid if the remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with zero to (N−1) bytes of the constant data
摘要翻译： 对由数据字节的可变多项（M）组成的二进制数字信号执行循环冗余码检查的装置包括缓冲寄存器，用于连续地临时存储每个由整数（N）个字节组成的段。 每个连续段被加载到循环冗余校验器中，循环冗余校验器在执行数字信号的多项式除法之后产生余数。 当最后一个段中的数字信号的字节数小于最后一个段用常数数据填充的整数多个（N）时。 如果余数匹配多个预定余数中的任一个，则每个对应于检验器的操作的有效数字信号以0到（N-1）个字节的恒定数据为准，则该信号被认为是有效的
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9.发明授权Communication switch including input bandwidth throttling to reduce output congestion 有权通信交换机包括输入带宽限制，以减少输出拥塞公开(公告)号：US06667985B1
公开(公告)日：2003-12-23
申请号：US09386481
申请日：1999-08-31
IPC分类号： H04L1228
CPC分类号： H04L49/508 , H04L47/10 , H04L47/26 , H04L47/29 , H04L47/30 , H04L49/30 , H04L49/3009 , H04L49/503 , H04L2012/5635 , H04L2012/5637 , H04L2012/5683
摘要： A network switch maintains transmit queues and for each transmit queue a table which identifies the contributions of traffic received at the ingress ports to that queue. When a queue is too long, a pause frame is dispatched from a selected one of the ingress ports. The ingress port may be selected as that making the greatest contribution to the transmit queue. However, a control algorithm allows ports carrying high priority traffic to be excluded from the selection.
摘要翻译： 网络交换机维护发送队列，并为每个发送队列维护标识在入口端口处接收到的流量对该队列的贡献的表。 当队列太长时，会从所选入口端口中分派一个暂停帧。 可以选择入口端口作为对发送队列做出最大贡献的入口端口。 然而，控制算法允许携带高优先级流量的端口从选择中排除。
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10.发明授权公开(公告)号：US06999452B1
公开(公告)日：2006-02-14
申请号：US09511118
申请日：2000-02-23
CPC分类号： H04L12/42 , H04L49/201 , H04L49/351 , H04L49/354
摘要： A packet-switched network system comprises a multiplicity of multi-port network units each of which has first and second ports and other ports and transmission links coupling the first and second ports of said unit in a closed ring. The first and second ports and transmission links support duplex transmission of Ethernet data packets. Each unit transmits from said first and second ports packets including selected information enabling on reception of a packet at any of the units a determination of a number of hops from unit to unit around said ring said packet has made. Each unit has a forwarding database and in response to the said selected information controls the transmission of said packets in two directions around said ring, and each unit causes discard of packets which have according to said selected information circumnavigated the ring.
摘要翻译： 分组交换网络系统包括多个多端口网络单元，每个多端口网络单元具有第一和第二端口以及以闭环形式将所述单元的第一和第二端口耦合的其它端口和传输链路。 第一和第二端口和传输链路支持以太网数据包的双工传输。 每个单元从所述第一和第二端口发送包括所选择的信息的分组，所述信息使得能够在任何单元上接收到分组的分组，所述分组在所述分组已经做出的所述环周围的单元到单元的跳数的确定。 每个单元具有转发数据库，并且响应于所述选择的信息控制所述分组在所述环周围的两个方向的传输，并且每个单元导致根据所述选择的信息循环环的分组丢弃。
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