公开(公告)号：US4406710A

公开(公告)日：1983-09-27

申请号：US311684

申请日：1981-10-15

申请人： Roderick D. Davies ,  David B. Scott

发明人： Roderick D. Davies ,  David B. Scott

IPC分类号： H01L21/033 ,  H01L21/8238 ,  H01L21/265 ,  B01J17/00

CPC分类号： H01L21/8238 ,  H01L21/033

摘要： CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region.Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative doping effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.

摘要翻译： 仅使用单个掩蔽步骤形成两种导电类型的CMOS源极/漏极区域。 一种掺杂剂被施加到两种类型的源极/漏极区域，并且第二掺杂剂以更高的剂量和能量被施加到仅一种类型的源极/漏极区域。 优选地，硼和砷用作硅中的掺杂剂，因为协同掺杂效应导致反掺杂的源/漏区中的硼完全包含在砷扩散内。

公开(公告)号：US4420344A

公开(公告)日：1983-12-13

申请号：US311713

申请日：1981-10-15

申请人： Roderick D. Davies ,  David B. Scott

发明人： Roderick D. Davies ,  David B. Scott

IPC分类号： H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/263 ,  H01L21/26

CPC分类号： H01L21/823814 ,  H01L21/033 ,  H01L27/0928

摘要： CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks. In addition, positive resists may be used in practicing the present invention.

摘要翻译： 仅使用单个掩蔽步骤形成两种导电类型的CMOS源极/漏极区域。 一种掺杂剂被施加到两种类型的源极/漏极区域，并且第二掺杂剂以更高的剂量和能量被施加到仅一种类型的源极/漏极区域。 优选地，硼和砷用作硅中的掺杂剂，因为协同扩散效应导致反掺杂源/漏区中的硼完全包含在砷扩散内。 为了避免在氯蚀刻下重掺杂多晶硅的不规则蚀刻特性，在P +源极/漏极注入期间，用于图案栅极和栅极级互连的图案化的光致抗蚀剂保留在适当的位置。 因此，可以使用中等掺杂的N型多晶硅，因为它不被P +植入物暴露于补偿。 由于不需要P +源极/漏极掩模，因此不会产生双层光刻胶结构，因此无需重新制作。 此外，在实施本发明时可以使用正性抗蚀剂。

公开(公告)号：US4476482A

公开(公告)日：1984-10-09

申请号：US377759

申请日：1982-05-13

申请人： David B. Scott ,  Roderick D. Davies ,  Yee-Chaung See

发明人： David B. Scott ,  Roderick D. Davies ,  Yee-Chaung See

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L27/092 ,  H01L23/48 ,  H01L29/04 ,  H01L29/46 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/0928

摘要： In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

摘要翻译： 在CMOS器件的制造中，氧化物被蚀刻掉离开多晶硅栅极级互连，并且需要与要连接多晶硅栅极级互连的导电类型的源极或漏极区域。 然后沉积金属，并且形成硅化物以将栅极级互连件连接到相应的源极和漏极区域。 为了确保硅化物连接的连续性，栅极级互连下方的栅极氧化物通过湿式蚀刻工艺略微下切，另外的多晶硅整体平坦地沉积，并且附加的多晶硅被各向异性地蚀刻，使得其从除了 栅极级互连之下的底切区域因此存在于多晶硅栅极级互连件和相应的源极和漏极区域之间的硅的连续表面，硅的连续表面从中生长连续的硅化物层。 因此，产生自对准的触点，并且不产生不需要的pn结。

公开(公告)号：US4374700A

公开(公告)日：1983-02-22

申请号：US268201

申请日：1981-05-29

申请人： David B. Scott ,  Roderick D. Davies ,  Yee-Chaung See

发明人： David B. Scott ,  Roderick D. Davies ,  Yee-Chaung See

IPC分类号： H01L27/092 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/308 ,  H01L21/24 ,  H01L21/283

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/0928

摘要： In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

摘要翻译： 在CMOS器件的制造中，氧化物被蚀刻掉离开多晶硅栅极级互连，并且需要与要连接多晶硅栅极级互连的导电类型的源极或漏极区域。 然后沉积金属，并且形成硅化物以将栅极级互连件连接到相应的源极和漏极区域。 为了确保硅化物连接的连续性，栅极级互连下方的栅极氧化物通过湿蚀刻工艺略微削弱，另外的多晶硅整体平坦地沉积，并且附加多晶硅被静电蚀刻，使得其从除了 栅极级互连之下的底切区域因此存在于多晶硅栅极级互连件和相应的源极和漏极区域之间的硅的连续表面，硅的连续表面从中生长连续的硅化物层。 因此，产生自对准的触点，并且不产生不需要的pn结。

公开(公告)号：US4418094A

公开(公告)日：1983-11-29

申请号：US353994

申请日：1982-03-02

申请人： Yee-Chaung See ,  Roderick D. Davies ,  Dennis C. Hartman

发明人： Yee-Chaung See ,  Roderick D. Davies ,  Dennis C. Hartman

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L27/00

CPC分类号： H01L21/76216 ,  H01L21/31116 ,  H01L21/32137

摘要： Direct Moat Isolation for VLSI integrated circuit structures is formed by growing oxide over the entire substrate area, and then cutting windows in the oxide, using an anisotropic polymer-free oxide etch, where moat regions are to be formed. To prevent polysilicon filamentation, gate patterning is performed with an extremely selective polysilicon etch. The combination of these processing steps permits a direct moat isolation device fabrication process which is insensitive to the oxide sidewall angle, increasing yield and permitting extremely compact isolation structures to be formed.

摘要翻译： VLSI集成电路结构的直接护城河隔离是通过在整个基板区域上生长氧化物，然后使用各向异性聚合物氧化物蚀刻，在其中形成护环区域来切割氧化物中的窗口而形成的。 为了防止多晶硅细化，栅极图案化是通过极其选择性的多晶硅蚀刻进行的。 这些处理步骤的组合允许对氧化物侧壁角度不敏感的直接沟槽隔离装置制造工艺，增加产量并允许形成非常紧凑的隔离结构。