公开(公告)号：US08455875B2

公开(公告)日：2013-06-04

申请号：US12776829

申请日：2010-05-10

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/12

CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

公开(公告)号：US20110272762A1

公开(公告)日：2011-11-10

申请号：US12776829

申请日：2010-05-10

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

摘要翻译： 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

公开(公告)号：US08691697B2

公开(公告)日：2014-04-08

申请号：US12943956

申请日：2010-11-11

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US08564069B1

公开(公告)日：2013-10-22

申请号：US13590212

申请日：2012-08-21

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

摘要翻译： 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

公开(公告)号：US08299530B2

公开(公告)日：2012-10-30

申请号：US12717375

申请日：2010-03-04

申请人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US08809994B2

公开(公告)日：2014-08-19

申请号：US13316104

申请日：2011-12-09

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/70

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US20120306049A1

公开(公告)日：2012-12-06

申请号：US13153538

申请日：2011-06-06

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/20 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US20120305998A1

公开(公告)日：2012-12-06

申请号：US13118881

申请日：2011-05-31

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  David M. Fried ,  Byeong Kim ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L29/92 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1203

摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

摘要翻译： 在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料 的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。 可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

公开(公告)号：US20110215412A1

公开(公告)日：2011-09-08

申请号：US12717375

申请日：2010-03-04

申请人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US08846470B2

公开(公告)日：2014-09-30

申请号：US13153538

申请日：2011-06-06

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242 ,  H01L49/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/74 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

摘要： A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

摘要翻译： 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。