公开(公告)号：US07625795B2

公开(公告)日：2009-12-01

申请号：US11217742

申请日：2005-09-01

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 集装箱电容器结构及其施工方法。 蚀刻掩模和蚀刻用于暴露结构的电极（“底部电极”）的外表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，其可用于形成额外的电容。 电容器电介质和顶电极分别形成在第一电极的内表面和外表面的两个部分上并与其相邻。 第一电极和第二电极两者共同的表面积仅通过使用内表面增加，提供额外的电容而不减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 电容器电介质和第二电极部分的清除可以在衬底组件的上部位置进行，与在接触通孔的底部位置处的清除相反。

公开(公告)号：US07579235B2

公开(公告)日：2009-08-25

申请号：US11545252

申请日：2006-10-10

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

公开(公告)号：US06753565B1

公开(公告)日：2004-06-22

申请号：US09652998

申请日：2000-08-31

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC: H01L27108

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US06395600B1

公开(公告)日：2002-05-28

申请号：US09389661

申请日：1999-09-02

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC: H01L218242

CPC classification number: H01L27/10888 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/91

Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

公开(公告)号：US06329263B1

公开(公告)日：2001-12-11

申请号：US09653259

申请日：2000-08-31

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC: H01L2120

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US5680350A

公开(公告)日：1997-10-21

申请号：US355752

申请日：1994-12-14

Applicant: Roger R. Lee

Inventor： Roger R. Lee

IPC: G11C16/16 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404

Abstract: This invention constitutes a method for narrowing threshold voltage distribution among the individual cells of a block erased flash memory array by firstly, preprogramming cells within the block be erased to a level of saturation using hot electron injection to drive a surplus of electrons into the floating gate of each cell; secondly, subjecting all cells with the block to a first erase pulse which causes the surplus electrons within the floating gate of each cell to be driven into the cell's source region via Fowler-Nordheim tunneling, with the erase pulse being of sufficient length to erase every cell within the block; thirdly, subjecting all cells within the block to a word line stress step or a soft programming step, by means of which some electrons are driven back into the floating gate of each cell via Fowler-Nordheim tunneling or hot electron injection, respectively; and, fourthly, subjecting all cells within the block to a second erase pulse, the second erase pulse being at least an order of magnitude shorter than the first erase pulse. Use of the second erase pulse following the word line stress step not only shifts the threshold voltage distribution to a somewhat lower level, but also compresses the distribution. Since compression on the high side of the curve is greater than on the low side, the length of the second erase pulse can be tailored to fit the characteristics of a particular flash memory.

Abstract translation: 本发明构成了通过首先将块内的单元预编程到使用热电子注入的饱和水平以将剩余的电子驱动到浮置栅极内的方式来缩小块擦除闪存阵列的各个单元之间的阈值电压分布的方法 的每个细胞; 其次，使具有块的所有单元经受第一擦除脉冲，其使得每个单元的浮置栅极内的剩余电子通过Fowler-Nordheim隧道驱动进入电池的源极区域，其中擦除脉冲具有足够的长度以擦除每个 块内的单元格; 第三，对块内的所有单元进行字线应力步骤或软编程步骤，借助于这些步骤，一些电子分别通过Fowler-Nordheim隧穿或热电子注入被驱回每个单元的浮动栅极; 以及第四，使所述块内的所有单元对第二擦除脉冲进行处理，所述第二擦除脉冲比所述第一擦除脉冲短至少一个数量级。 使用字线应力步骤之后的第二擦除脉冲不仅将阈值电压分布移动到稍低的水平，而且压缩分布。 由于曲线的高侧的压缩大于在低侧的压缩，所以可以调整第二擦除脉冲的长度以适应特定的闪速存储器的特性。

公开(公告)号：US5559742A

公开(公告)日：1996-09-24

申请号：US393578

申请日：1995-02-23

Applicant: Roger R. Lee ,  Fernando Gonzalez

Inventor： Roger R. Lee ,  Fernando Gonzalez

IPC: G11C16/16 ,  G11C29/00 ,  G11C11/40

CPC classification number: G11C29/82 ,  G11C16/16

Abstract: A flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary row line are programmed and the cells along the redundant row line are selectively programmed. The primary row line is bypassed during any read cycle.

Abstract translation: 闪存阵列包括主行线和冗余行线，每行具有存储单元。 访问闪存阵列的方法包括对所有所述存储单元进行预编程。 接下来，所有存储单元都被同时擦除。 随后，沿着主行行的所有存储单元被编程，并且沿着冗余行线的单元格被有选择地编程。 在任何读取周期中，主行行都被旁路。

公开(公告)号：US5208177A

公开(公告)日：1993-05-04

申请号：US832561

申请日：1992-02-07

Applicant: Roger R. Lee

Inventor： Roger R. Lee

IPC: H01L21/265 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/11206 ,  H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002

Abstract: The present invention provides improved programmability of antifuse elements by utilizing local enhancement of an underlying diffusion region. During an existing fabrication of a semiconductor device using antifuse elements after the access lines (usually word lines) are formed, a self-aligning trench is etched between two neighboring access lines thereby severing an underlying diffusion region. Following an etch back of the access lines' spacers a low energy, heavy dose implant dopes the exposed edges of the diffusion region resulting from the spacer etch back, as well as the bottom of the trench. An antifuse dielectric is formed followed by placing of a second conductive access line (usually the source lines) thus filling the trench to serve as the programmable antifuse element. The heavily doped areas in the diffusion region will now allow a reduction in programming voltage level, while providing a sufficient rupture of the antifuse dielectric.

Abstract translation: 本发明通过利用潜在扩散区域的局部增强来提供反熔丝元件的改进的可编程性。 在形成在接入线（通常是字线）之后使用反熔丝元件的半导体器件的现有制造期间，在两个相邻的接入线之间蚀刻自对准沟槽，从而切割下面的扩散区域。 在接入线的间隔物的蚀刻之后，低能量的重剂量注入掺杂由间隔物回蚀而产生的扩散区域的暴露边缘以及沟槽的底部。 形成反熔丝电介质，然后放置第二导电接入线（通常为源极线），从而填充沟槽以用作可编程反熔丝元件。 扩散区域中的重掺杂区域现在将允许减少编程电压电平，同时提供反熔丝电介质的充分破裂。

公开(公告)号：US07192829B2

公开(公告)日：2007-03-20

申请号：US09118359

申请日：1998-07-17

Applicant: J. Dennis Keller ,  Roger R. Lee

Inventor： J. Dennis Keller ,  Roger R. Lee

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4925

Abstract: Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.

Abstract translation: 描述了浮栅晶体管及其形成方法。 在一个实施方式中，在衬底上形成浮栅。 浮动门具有内部第一部分和外部第二部分。 在内部第一部分中提供增强电导的杂质以比外部第二部分中的增强电导率的杂质更大的浓度。 在另一实施方案中，浮栅由第一导电掺杂半导体材料层和基本上未掺杂的半导体材料的第二层形成。 在另一实施方案中，浮栅由具有第一平均晶粒尺寸的第一材料和具有大于第一平均晶粒尺寸的第二平均晶粒尺寸的第二材料形成。

公开(公告)号：US06693319B1

公开(公告)日：2004-02-17

申请号：US09652929

申请日：2000-08-31

Applicant: D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

Inventor： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC: H01L27108

CPC classification number: H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

Abstract translation: 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。