公开(公告)号：US07160785B1

公开(公告)日：2007-01-09

申请号：US09652999

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US06528834B1

公开(公告)日：2003-03-04

申请号：US09653005

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

公开(公告)号：US5513137A

公开(公告)日：1996-04-30

申请号：US393584

申请日：1995-02-23

申请人： Roger R. Lee ,  Fernando Gonzalez

发明人： Roger R. Lee ,  Fernando Gonzalez

IPC分类号： G11C29/00 ,  G11C11/34

CPC分类号： G11C29/82

摘要： A flash programmable memory device comprises first and second row lines each having memory elements therealong with the second conductive line functionally replacing the first conductive line. The memory device further includes a first program circuit for programming the memory elements along the first row line, and a second program circuit for programming memory elements along the second row line. A read circuit bypasses the first conductive line during all read cycles and reads the memory elements along the second row line.

摘要翻译： 闪存可编程存储器件包括第一和第二行线，每条线具有存储元件，第二导线在功能上替代第一导线。 存储装置还包括用于沿着第一行线对存储元件进行编程的第一编程电路和用于沿着第二行线对存储元件进行编程的第二编程电路。 读取电路在所有读取周期期间绕过第一导线，并沿着第二行线读取存储器元件。

公开(公告)号：US5244826A

公开(公告)日：1993-09-14

申请号：US870606

申请日：1992-04-16

申请人： Fernando Gonzalez ,  Roger R. Lee

发明人： Fernando Gonzalez ,  Roger R. Lee

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/87

摘要： An array of finned memory cell capacitors on a semiconductor substrate includes: a) an array of electrically insulated word lines atop a semiconductor substrate; b) first and second active regions adjacent the word lines; c) capacitor storage nodes electrically connecting with the first active regions, individual capacitor storage nodes including: i) a layer of first conductive material conductively connecting with a first active region, the layer of first conductive material having opposed outer lateral edges, and ii) a layer of conductively doped storage node polysilicon overlying and conductively connecting with the layer of first conductive material, the storage node polysilicon projecting laterally outward beyond the outer lateral edges of the first conductive material to define opposing storage node capacitor fins projecting laterally above adjacent word lines; d) a layer of capacitor dielectric electrically connecting with the storage node capacitor fins; e) a layer of electrically conductive cell polysilicon electrically connecting with the capacitor dielectric layer; and f) bit lines electrically connecting with the second active regions. The invention also includes a method of forming memory cell capacitors.

摘要翻译： 半导体衬底上的鳍状存储单元电容器阵列包括：a）半导体衬底顶部的电绝缘字线阵列; b）与字线相邻的第一和第二有源区; c）与第一有源区电连接的电容器存储节点，各个电容器存储节点包括：i）与第一有源区导电连接的第一导电材料层，第一导电材料层具有相对的外侧边缘，以及ii） 导电掺杂存储节点多晶硅层覆盖并与第一导电材料层导电连接，存储节点多晶硅横向向外突出超出第一导电材料的外侧边缘，以限定在相邻字线之上横向突出的相对的存储节点电容器鳍片 ; d）与存储节点电容器散热片电连接的电容器电介质层; e）与电容器介电层电连接的导电单元多晶硅层; 以及f）与第二有源区域电连接的位线。 本发明还包括形成存储单元电容器的方法。

公开(公告)号：US5192703A

公开(公告)日：1993-03-09

申请号：US786242

申请日：1991-10-31

申请人： Roger R. Lee ,  Fernando Gonzalez

发明人： Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： The invention is a product and method for forming the same comprising a storage contact capacitor of a DRAM device wherein the storage node capacitor plate comprises first and second capacitor portions. The first portion is a self-aligned Tungsten and TiN core. In a first embodiment the second portion is a storage node polysilicon deposited and subjected to an insitu phosphorus diffusion doping. In a second embodiment the second portion comprises tungsten fingers formed elevationally and horizontally to overlie the tungsten and TiN core. Portions of TiN provide spacing between adjacent tungsten fingers. An upper polysilicon layer functions as the upper capacitor plate and is insulated from the lower capacitor plate by a dielectric layer.

摘要翻译： 本发明是一种用于形成DRAM器件的存储接触电容器的产品和方法，其中存储节点电容器板包括第一和第二电容器部分。 第一部分是自对准钨和钛核。 在第一实施例中，第二部分是沉积并经受现场磷扩散掺杂的存储节点多晶硅。 在第二实施例中，第二部分包括形成为垂直和水平的钨指，以覆盖钨和TiN芯。 TiN的一部分提供相邻钨指之间的间距。 上部多晶硅层用作上部电容器板，并通过介电层与下部电容器板绝缘。

公开(公告)号：US06693319B1

公开(公告)日：2004-02-17

申请号：US09652929

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US06333240B1

公开(公告)日：2001-12-25

申请号：US09652497

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L2120

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

公开(公告)号：US5714414A

公开(公告)日：1998-02-03

申请号：US699551

申请日：1996-08-19

申请人： Roger R. Lee ,  Fernando Gonzalez

发明人： Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes providing a semiconductor substrate having field and active area regions; forming masking material over the active area region and leaving the field region exposed, the masking material comprising first, second and third layers, and having a sidewall; exposing the semiconductor substrate to first oxidation conditions effective to form field isolation oxide of a first thickness over the exposed field region; forming an etch stop material layer over the sidewall; removing at least a portion of the third layer selectively relative to the etch stop material layer; and subjecting the semiconductor substrate to second oxidation conditions effective to grow the field isolation oxide to a second thickness on the exposed field region of the semiconductor substrate.

公开(公告)号：US5262662A

公开(公告)日：1993-11-16

申请号：US926726

申请日：1992-08-06

申请人： Fernando Gonzalez ,  Roger R. Lee

发明人： Fernando Gonzalez ,  Roger R. Lee

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01G4/06

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91 ,  Y10S257/915

摘要： A dynamic random access memory (DRAM) storage cell having a storage contact capacitor comprising a tungsten and TiN storage node capacitor plate and the method for fabricating the same. At least a portion of the storage node capacitor plate is formed vertically in the DRAM. The TiN is controllably etched to increase the area of the storage node capacitor plate. An upper poly layer functions as the cell plate and is insulated from the storage node capacitor plate by a dielectric layer.

摘要翻译： 具有包括钨和TiN存储节点电容器板的存储接触电容器的动态随机存取存储器（DRAM）存储单元及其制造方法。 存储节点电容器板的至少一部分在DRAM中垂直形成。 可控地蚀刻TiN以增加存储节点电容器板的面积。 上多层用作电池板，并通过电介质层与存储节点电容器板绝缘。

公开(公告)号：US08124491B2

公开(公告)日：2012-02-28

申请号：US12547197

申请日：2009-08-25

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 公开了一种容器电容器结构及其构造方法。 蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。 因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。 有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。