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    Line mask defined active areas for 8F2 dram cells with folded bit lines and deep trench patterns
    1.
    发明申请
    Line mask defined active areas for 8F2 dram cells with folded bit lines and deep trench patterns 有权
    线路掩模定义了具有折叠位线和深沟槽图案的8F2显示单元的有源区域

    公开(公告)号：US20050176197A1

    公开(公告)日：2005-08-11

    申请号：US10774827

    申请日：2004-02-09

    申请人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    发明人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

    摘要翻译： 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

    Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns
    2.
    发明授权
    Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns 有权
    线掩模定义了具有折叠位线和深沟槽图案的8F2 DRAM单元的有源区

    公开(公告)号：US07244980B2

    公开(公告)日：2007-07-17

    申请号：US10774827

    申请日：2004-02-09

    申请人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    发明人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

    摘要翻译： 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

    Modified vertical MOSFET and methods of formation thereof
    6.
    发明授权
    Modified vertical MOSFET and methods of formation thereof 失效
    改进的垂直MOSFET及其形成方法

    公开(公告)号：US06541810B2

    公开(公告)日：2003-04-01

    申请号：US09896741

    申请日：2001-06-29

    申请人： Ramachandra Divakaruni ,  Prakash Dev ,  Rajeev Malik ,  Larry Nesbit

    发明人： Ramachandra Divakaruni ,  Prakash Dev ,  Rajeev Malik ,  Larry Nesbit

    IPC分类号： H01L27108

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891

    摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

    摘要翻译： 用于形成动态随机存取存储器的垂直MOSFET结构包括包括一个或多个氮化硅间隔物的栅堆叠结构; 设置在阵列沟槽中的垂直栅极多晶硅区域，其中所述垂直栅极多晶硅区域包括一个或多个氮化硅间隔物; 位线扩散区; 与阵列沟槽接壤的浅沟槽隔离区; 并且其中栅极堆叠结构设置在垂直栅极多晶硅区域上，使得栅极堆叠结构和垂直栅极多晶硅区域的氮化硅间隔物与位线扩散区域和浅沟槽隔离区域形成无边界接触。 垂直栅极多晶硅通过氮化物间隔物从位线扩散和浅沟槽隔离区域隔离，这提供了减少的位线电容并且减少了位线扩散到垂直栅极短路的入射。

    Patterned strained semiconductor substrate and device
    7.
    发明授权
    Patterned strained semiconductor substrate and device 有权
    图形应变半导体衬底和器件

    公开(公告)号：US09515140B2

    公开(公告)日：2016-12-06

    申请号：US12015272

    申请日：2008-01-16

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8234

    CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

    摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

    摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

    Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates
    8.
    发明授权
    Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates 有权
    用于在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构

    公开(公告)号：US08703552B2

    公开(公告)日：2014-04-22

    申请号：US13419624

    申请日：2012-03-14

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni

    IPC分类号： H01L27/06 ,  H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

    摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

    摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。

    High capacitance trench capacitor
    9.
    发明授权
    High capacitance trench capacitor 有权
    高电容沟槽电容

    公开(公告)号：US08492818B2

    公开(公告)日：2013-07-23

    申请号：US12881481

    申请日：2010-09-14

    申请人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

    发明人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

    IPC分类号： H01L27/108

    CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10867 ,  H01L29/945

    摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

    摘要翻译： 双节点介质沟槽电容器包括在沟槽中形成的一叠层。 层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。 双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。 第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。 双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

    Electrical Fuse Formed By Replacement Metal Gate Process
    10.
    发明申请
    Electrical Fuse Formed By Replacement Metal Gate Process 有权
    通过更换金属浇口工艺形成的电保险丝

    公开(公告)号：US20120256267A1

    公开(公告)日：2012-10-11

    申请号：US13080019

    申请日：2011-04-05

    申请人： Ying Li ,  Ramachandra Divakaruni

    发明人： Ying Li ,  Ramachandra Divakaruni

    IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L21/28

    CPC分类号： H01L23/5256 ,  H01L27/0629 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.

    摘要翻译： 提供一种用于制造电熔丝和场效应晶体管的方法，所述场效应晶体管具有金属栅极，该金属栅极包括从覆盖衬底的电介质区域中的第一和第二开口去除材料，其中第一开口与衬底的有源半导体区域对准， 并且所述第二开口与所述衬底的隔离区域对准，并且所述有源半导体区域包括与所述第一开口的边缘相邻的源极区域和漏极区域。 可以形成电熔丝，其具有填充第二开口的熔丝元件，熔丝元件是单一导电材料的整体区域，金属或金属的导电化合物。 可以形成在第一开口内延伸的金属栅极，以限定包括金属栅极和有源半导体区域的场效应晶体管（FET）。