Apparatus for memory bus tuning and methods therefor
    4.
    发明授权
    Apparatus for memory bus tuning and methods therefor 有权
    用于存储器总线调谐的装置及其方法

    公开(公告)号:US06496911B1

    公开(公告)日:2002-12-17

    申请号:US09165954

    申请日:1998-10-02

    IPC分类号: G06F1200

    CPC分类号: G06F13/4239 G06F13/4072

    摘要: An apparatus and method for memory bus tuning are implemented. A plurality of drivers having a plurality of selectable drive levels are coupled to a memory bus. The memory bus is connected to a memory device which may have a variable amount of memory, which may be in the form of dual-in-line memory modules (DIMM). A drive level is selected in response to a determination of the amount of memory included in the memory device. A register operable for receiving a data value corresponding to the amount of memory is coupled to the drivers, the drive level being selected thereby.

    摘要翻译: 实现用于存储器总线调谐的装置和方法。 具有多个可选驱动电平的多个驱动器耦合到存储器总线。 存储器总线连接到可能具有可变量的存储器的存储器件,存储器可以是双列直插存储器模块(DIMM)的形式。 响应于确定包括在存储器件中的存储器的量来选择驱动器电平。 可操作用于接收与存储器量相对应的数据值的寄存器耦合到驱动器,从而选择驱动级。

    Bus interface logic system
    7.
    发明授权
    Bus interface logic system 失效
    总线接口逻辑系统

    公开(公告)号:US5768550A

    公开(公告)日:1998-06-16

    申请号:US560758

    申请日:1995-11-21

    CPC分类号: G06F13/36 G06F13/4027

    摘要: A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.

    摘要翻译: 一种通过提供用于存储数据的缓冲器和用于将并发地址和数据总线事务划分为地址总线事务以及数据总线事务的控制逻辑来同步具有不同总线事务的两个处理器之间的数据传输的系统和方法。 在读取操作期间,请求设备在进入数据总线事务之前被迫等待数据可用性。 在写入操作期间,通过使用有效地将地址事务与数据事务分离的存储机制来延迟数据总线事务。 本发明还提供了在输入/输出设备和存储设备之间的直接存储器访问飞越操作。 这些操作通过将二次总线与系统总线隔离并允许目标设备在系统总线上可用时捕获所请求的数据来实现。

    Method and system for managing peripheral connection wakeup in a processing system supporting multiple virtual machines
    9.
    发明授权
    Method and system for managing peripheral connection wakeup in a processing system supporting multiple virtual machines 有权
    在支持多个虚拟机的处理系统中管理外围连接唤醒的方法和系统

    公开(公告)号:US07992023B2

    公开(公告)日:2011-08-02

    申请号:US11962068

    申请日:2007-12-20

    IPC分类号: G06F13/14

    CPC分类号: G06F1/3209

    摘要: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

    摘要翻译: 用于在支持多个虚拟机的处理系统中管理外围连接唤醒信令的方法和系统提供了一种机制,通过该机制,具有系统唤醒能力的外围设备的所有权在虚拟机之间传送。 电源管理事件信号连接到服务处理器输入,该服务处理器输入又传送信号管理程序以将唤醒活动引导到虚拟机最后执行的特定逻辑分区。 管理程序然后可以确定是否唤醒整个系统或其部分,并且可以将电源管理事件引导到适当的虚拟机。 特别地,外设可以是支持Wake-On-LAN功能的以太网适配器。 通过系统功率循环确保的状态初始化是通过控制待机电源的电源,或者在某些情况下通过强制唤醒信令连接的断开/重新连接的指示来提供的。

    Method for estimating total power requirement in a computer system
    10.
    发明授权
    Method for estimating total power requirement in a computer system 失效
    估算计算机系统总功率需求的方法

    公开(公告)号:US07496772B1

    公开(公告)日:2009-02-24

    申请号:US12041669

    申请日:2008-03-04

    申请人: Thoi Nguyen

    发明人: Thoi Nguyen

    IPC分类号: G06F1/00 G06F1/32 G06F11/30

    CPC分类号: G06F1/3203 G06F9/4401

    摘要: In a computer system having a power supply, processor, and additional subcomponents that are powered by the power supply, a method for estimating the total power requirements of the system under a variety of operating modes and configurations. In an exemplary embodiment, information concerning power requirements for each subcomponent under its operating modes is stored within non-volatile memory within the subcomponents. This information is accessed by the processor during the boot sequence, and if the information is not available, substitute information is provided. The compiled information is tabulated to compute the estimated total power requirement of the current hardware configuration. A display of this information, along with configuration selection rules, enables the user to select alternative operating modes and configurations and to show the resulting estimated power requirements.

    摘要翻译: 在具有由电源供电的电源,处理器和附加子组件的计算机系统中,一种用于在各种操作模式和配置下估计系统的总功率需求的方法。 在示例性实施例中,关于在其操作模式下的每个子组件的功率需求的信息被存储在子组件内的非易失性存储器中。 该信息在引导顺序期间由处理器访问,如果信息不可用,则提供替代信息。 编制的信息被列表以计算当前硬件配置的估计总功率需求。 该信息的显示以及配置选择规则使得用户能够选择替代的操作模式和配置并且显示所得的估计的功率需求。