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1.发明申请公开(公告)号：US20090193233A1
公开(公告)日：2009-07-30
申请号：US12043747
申请日：2008-03-06
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。
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2.发明授权公开(公告)号：US07370177B2
公开(公告)日：2008-05-06
申请号：US10424527
申请日：2003-04-25
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。
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3.发明授权公开(公告)号：US07949859B2
公开(公告)日：2011-05-24
申请号：US12043747
申请日：2008-03-06
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30189 , G06F9/383 , G06F9/3842
摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.
摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。
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公开(公告)号：US08387065B2
公开(公告)日：2013-02-26
申请号：US12425343
申请日：2009-04-16
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3842
摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.
摘要翻译： 一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。 该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。 该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。
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公开(公告)号：US07996564B2
公开(公告)日：2011-08-09
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译： 分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器 由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。 在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。 本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问 数据中心为远程存储器的节点ID。
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公开(公告)号：US20100268788A1
公开(公告)日：2010-10-21
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F15/167 , G06F9/46 , G06F12/00 , G06F12/10
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译： 分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器 由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。 在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。 本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问 数据中心为远程存储器的节点ID。
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公开(公告)号：US07937570B2
公开(公告)日：2011-05-03
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: an asynchronous memory mover (AMM) store (ST) instruction that initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and a LD CMP instruction for checking a status of an AMM operation.
摘要翻译： 数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：异步存储器移动器（AMM）存储（ST）指令，其启动异步存储器移动操作，其从具有第一存储器位置的第一存储器位置移动数据， 具有第二实际地址的第二存储器位置的第一实际地址：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA还提供用于在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及用于检查AMM操作的状态的LD CMP指令。
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公开(公告)号：US20090198975A1
公开(公告)日：2009-08-06
申请号：US12024546
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/315
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/3834 , G06F9/3885
摘要： A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: (1) an asynchronous memory mover (AMM) store (ST) instruction initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides (2) an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and (3) a LD CMP instruction for checking a status of an AMM operation.
摘要翻译： 数据处理系统具有处理器，存储器和指令集架构（ISA），其包括：（1）异步存储器移动器（AMM）存储器（ST）指令发起异步存储器移动操作，其将数据从第一存储器 具有通过以下方式具有第二实际地址的具有第一实际地址的位置：（a）首先使用源有效地址执行虚拟地址空间中的数据移动目的地有效地址; 和（b）当移动完成时，完成数据到第二存储器位置的物理移动，而与处理器无关。 ISA进一步提供（2）在完成AMM操作之前停止正在进行的AMM操作的AMM终止ST指令，以及（3）用于检查AMM操作状态的LD CMP指令。
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公开(公告)号：US06981128B2
公开(公告)日：2005-12-27
申请号：US10422664
申请日：2003-04-24
CPC分类号： G06F9/3834 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/3824 , G06F9/3851
摘要： In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.
摘要翻译： 在具有多个执行单元的系统中，排队等待指令进行高效的调度。 一个加载/存储单元（LSU）可以具有等待到实际地址的存储指令，并且第二LSU可以具有等待到同一实际地址的加载指令。 SMT系统具有原子存储四字（SQW）指令，数据路径仅为双倍宽，SQW需要两个周期才能完成。 SMT系统需要一种方法来防止存储重新排序队列（SRQ）STQ中的冲突。 一个线程的加载字（LW）的真实地址与第二个线程的SRQ中的实际地址进行比较。 如果具有与LW的实际地址匹配的实际地址的SQW没有提交两个双字，则第二个线程的LW被拒绝。
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公开(公告)号：US08356151B2
公开(公告)日：2013-01-15
申请号：US12024504
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/30043 , G06F12/0831 , G06F12/0862 , G06F12/1027
摘要： A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received.
摘要翻译： 在数据处理系统中执行的方法启动异步存储器移动（AMM）操作，由此处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并将AMM操作的参数转发到异步存储器 用于完成数据从第一存储器位置到第二存储器位置的物理移动的移动器逻辑。 处理器执行第二操作，其检查数据移动完成的状态，并返回指示状态的通知。 该通知表示状态，其中包括：数据移动进行中的一个; 数据移动完成; 数据移动部分完成; 无法执行数据移动; 以及出现翻译后备缓冲区无效条目（TLBIE）操作。 处理器响应于收到的通知发起一个或多个动作。
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