公开(公告)号：US07900027B2

公开(公告)日：2011-03-01

申请号：US12023913

申请日：2008-01-31

申请人： Ronald P. Hall ,  Michael Lance Karm ,  David Mui ,  Albert James Van Norstrand, Jr.

发明人： Ronald P. Hall ,  Michael Lance Karm ,  David Mui ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F9/40 ,  G06F9/312

CPC分类号： G06F9/30134 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3842

摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.

摘要翻译： 计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。 数据处理系统利用推测性推送并从链路堆栈弹出。 链路栈包括一组条目，并且每个条目包括一组状态位。 第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。 第一位被设置为指示第一条指令是有效指令。 第二位被设置为指示第一条指令被推测地推到链路栈上。 更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。

公开(公告)号：US20090198959A1

公开(公告)日：2009-08-06

申请号：US12023913

申请日：2008-01-31

申请人： Ronald P. Hall ,  Michael Lance Karm ,  David Mui ,  Albert James Van Norstrand, JR.

发明人： Ronald P. Hall ,  Michael Lance Karm ,  David Mui ,  Albert James Van Norstrand, JR.

IPC分类号： G06F9/315

CPC分类号： G06F9/30134 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3842

摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.

摘要翻译： 计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。 数据处理系统利用推测性推送并从链路堆栈弹出。 链路栈包括一组条目，并且每个条目包括一组状态位。 第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。 第一位被设置为指示第一条指令是有效指令。 第二位被设置为指示第一条指令被推测地推到链路栈上。 更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。

公开(公告)号：US08898441B2

公开(公告)日：2014-11-25

申请号：US13452854

申请日：2012-04-21

申请人： Giles Roger Frazier ,  Ronald P. Hall

发明人： Giles Roger Frazier ,  Ronald P. Hall

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/46 ,  G06F9/48 ,  G06F2209/5018

摘要： A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

摘要翻译： 第一硬件线程执行软件程序指令，指令第一硬件线程启动第二硬件线程。 因此，第一硬件线程识别由第一硬件线程可访问的一个或多个寄存器值。 接下来，第一硬件线程将所识别的寄存器值复制到由第二硬件线程可访问的一个或多个寄存器。 反过来，第二个硬件线程访问可访问寄存器中包含的复制寄存器值，并相应地执行软件代码。

公开(公告)号：US08612730B2

公开(公告)日：2013-12-17

申请号：US12796124

申请日：2010-06-08

申请人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

发明人： Ronald P. Hall ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Balaram Sinharoy ,  Zhong Liang Wang

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/327 ,  G06F11/3466 ,  G06F2201/865 ,  G06F2201/88

摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.

摘要翻译： 一种用于管理程序中的指令的运行的方法和数据处理系统。 数据处理系统的处理器接收监视单元的监视指令。 处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。 响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。 处理器将程序中指令的运行情况从主线程更改为辅助线程。

公开(公告)号：US20120072705A1

公开(公告)日：2012-03-22

申请号：US12886091

申请日：2010-09-20

申请人： Giles Roger Frazier ,  Ronald P. Hall

发明人： Giles Roger Frazier ,  Ronald P. Hall

IPC分类号： G06F9/38 ,  G06F9/455 ,  G06F9/30 ,  G06F12/02

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/46 ,  G06F9/48 ,  G06F2209/5018

摘要： A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

公开(公告)号：US07818544B2

公开(公告)日：2010-10-19

申请号：US12204865

申请日：2008-09-05

申请人： Christopher M. Abernathy ,  Kurt A. Feiste ,  Ronald P. Hall ,  Albert J. Van Norstrand, Jr.

发明人： Christopher M. Abernathy ,  Kurt A. Feiste ,  Ronald P. Hall ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F9/28

CPC分类号： G06F9/524

摘要： Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

摘要翻译： 提供了将处理器置于逐渐减速操作模式的机制。 逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。 处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

公开(公告)号：US08793474B2

公开(公告)日：2014-07-29

申请号：US12886091

申请日：2010-09-20

申请人： Giles Roger Frazier ,  Ronald P. Hall

发明人： Giles Roger Frazier ,  Ronald P. Hall

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/46 ,  G06F9/48 ,  G06F2209/5018

摘要： A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

公开(公告)号：US20120210102A1

公开(公告)日：2012-08-16

申请号：US13452854

申请日：2012-04-21

申请人： Giles Roger Frazier ,  Ronald P. Hall

发明人： Giles Roger Frazier ,  Ronald P. Hall

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/46 ,  G06F9/48 ,  G06F2209/5018

摘要： A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

摘要翻译： 第一硬件线程执行软件程序指令，指令第一硬件线程启动第二硬件线程。 因此，第一硬件线程识别由第一硬件线程可访问的一个或多个寄存器值。 接下来，第一硬件线程将所识别的寄存器值复制到由第二硬件线程可访问的一个或多个寄存器。 反过来，第二个硬件线程访问可访问寄存器中包含的复制寄存器值，并相应地执行软件代码。

公开(公告)号：US20120072707A1

公开(公告)日：2012-03-22

申请号：US12886149

申请日：2010-09-20

申请人： Richard Louis Arndt ,  Giles Roger Frazier ,  Ronald P. Hall

发明人： Richard Louis Arndt ,  Giles Roger Frazier ,  Ronald P. Hall

IPC分类号： G06F9/00

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/485

摘要： A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating.

摘要翻译： 处理器包括启动硬件线程，其启动第一辅助硬件线程以执行第一代码段。 接下来，启动硬件线程响应于启动第一辅助硬件线程而设置辅助线程执行指示符。 设置的辅助线程执行指示符指示辅助硬件线程是否正在执行。 第二辅助硬件线程启动并开始执行第二代码段。 反过来，启动硬件线程检测到辅助线程执行指示符的变化，这意味着第一辅助硬件线程和第二辅助硬件线程都被终止。 因此，启动硬件线程响应于两个辅助硬件线程终止来评估辅助硬件线程结果。

公开(公告)号：US20110283095A1

公开(公告)日：2011-11-17

申请号：US12778192

申请日：2010-05-12

申请人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

发明人： Ronald P. Hall ,  Hung Q. Le ,  Raul E. Silvera ,  Balaram Sinharoy

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30149 ,  G06F9/30189

摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

摘要翻译： 提供了将工作负载从主线程卸载到辅助线程的机制。 机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。 分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。 硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。 如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。 此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。