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1.发明授权Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates 失效将清除矢量从第一执行单元直接生成到多个执行单元的每个其他执行单元，以便阻止所有寄存器更新公开(公告)号：US08082423B2
公开(公告)日：2011-12-20
申请号：US11201683
申请日：2005-08-11
申请人： Christopher Michael Abernathy , Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
发明人： Christopher Michael Abernathy , Kurt Alan Feiste , David Scott Ray , David Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/3013 , G06F9/3859 , G06F9/3863 , G06F9/3885
摘要： A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.
摘要翻译： 提供了一种用于检测和处理微处理器系统中的指令齐平的方法和装置。 提供了一种分布在数据处理系统中的所有执行单元的刷新机制。 冲洗机构不需要中央收集点将刷新信号重新分配给执行单元。 每个单元生成一个刷新向量到所有其他执行单元，用于阻止刷新指令的寄存器更新。
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公开(公告)号：US20090070609A1
公开(公告)日：2009-03-12
申请号：US12269997
申请日：2008-11-13
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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公开(公告)号：US08051315B2
公开(公告)日：2011-11-01
申请号：US12269997
申请日：2008-11-13
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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4.发明申请SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIVE OPERATIONS 失效可扩展的链路堆栈控制方法，具有全面的支持用于分析操作公开(公告)号：US20090198959A1
公开(公告)日：2009-08-06
申请号：US12023913
申请日：2008-01-31
IPC分类号： G06F9/315
CPC分类号： G06F9/30134 , G06F9/30054 , G06F9/3806 , G06F9/3842
摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.
摘要翻译： 计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。 数据处理系统利用推测性推送并从链路堆栈弹出。 链路栈包括一组条目，并且每个条目包括一组状态位。 第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。 第一位被设置为指示第一条指令是有效指令。 第二位被设置为指示第一条指令被推测地推到链路栈上。 更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。
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5.发明授权Method and apparatus for delaying a load miss flush until issuing the dependent instruction 有权用于延迟负载奇偶校验的方法和装置，直到发出依赖指令公开(公告)号：US07953960B2
公开(公告)日：2011-05-31
申请号：US11252410
申请日：2005-10-18
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
摘要翻译： 流水线处理器具有在管线的发布阶段检测寄存器访问指令的存在的电路。 在稍后阶段发生的负载丢失可能导致寄存器访问指令被标记有相关位。 寄存器访问指令在流水线下进行，当达到flush阶段时，处理器检查相关的位并刷新寄存器访问指令。
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6.发明授权Scalable link stack control method with full support for speculative operations 失效可扩展的链路栈控制方法，完全支持投机操作公开(公告)号：US07900027B2
公开(公告)日：2011-03-01
申请号：US12023913
申请日：2008-01-31
CPC分类号： G06F9/30134 , G06F9/30054 , G06F9/3806 , G06F9/3842
摘要： A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and each entry comprises a set of state bits. A speculative push of a first instruction is received onto the data stack, and the first instruction is stored into a first entry of the set of entries. A first bit is set to indicate that the first instruction is a valid instruction. A second bit is set to indicate that the first instruction has been speculatively pushed onto the link stack. The link stack pointer control is updated to indicate that the first entry is a top-of-data stack entry.
摘要翻译： 计算机实现的方法，处理器芯片，计算机程序产品和管理链路栈的数据处理系统。 数据处理系统利用推测性推送并从链路堆栈弹出。 链路栈包括一组条目，并且每个条目包括一组状态位。 第一指令的推测推送被接收到数据堆栈上，并且第一指令被存储到该组条目的第一条目中。 第一位被设置为指示第一条指令是有效指令。 第二位被设置为指示第一条指令被推测地推到链路栈上。 更新链接堆栈指针控件以指示第一个条目是顶部数据堆栈条目。
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公开(公告)号：US07496776B2
公开(公告)日：2009-02-24
申请号：US10645024
申请日：2003-08-21
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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公开(公告)号：US07313673B2
公开(公告)日：2007-12-25
申请号：US11154158
申请日：2005-06-16
申请人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James Dement , Albert James Van Norstrand, Jr. , David Shippy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3009 , G06F9/3802
摘要： The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the block matches the length of the latency, so the pipeline can dispatch instructions from the blocked thread after the long latency condition is resolved. In one embodiment the dispatch-block signaling instruction is a modified OR instruction and in another embodiment it is a Nop instruction. By blocking one thread at dispatch, the processor can dispatch instructions from the other threads during the block.
摘要翻译： 本发明提供一种方法，计算机程序产品和用于在多线程处理器中调度线程的线程的装置，用于线程性能的细粒度控制。 多个线程在处理器中共享流水线。 因此，一个线程上的指令的长延迟条件可以阻止所有共享流水线的线程。 调度块信令指令在发送时阻止包含长延迟条件的线程。 块的长度与延迟的长度相匹配，因此，在长时间等待条件解决之后，流水线可以从阻塞的线程中分派指令。 在一个实施例中，调度块信令指令是经修改的OR指令，在另一实施例中是Nop指令。 通过在调度时阻止一个线程，处理器可以在块期间从其他线程分派指令。
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