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    SYSTEMS FOR REVERSE BIAS TRIM OPERATIONS IN NON-VOLATILE MEMORY
    3.
    发明申请
    SYSTEMS FOR REVERSE BIAS TRIM OPERATIONS IN NON-VOLATILE MEMORY 有权
    用于在非易失性存储器中反向偏移操作的系统

    公开(公告)号：US20080025078A1

    公开(公告)日：2008-01-31

    申请号：US11461431

    申请日：2006-07-31

    申请人： Roy E. Scheuerlein ,  Tanmay Kumar

    发明人： Roy E. Scheuerlein ,  Tanmay Kumar

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C11/56 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/72

    摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

    摘要翻译： 公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。 包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平处的第一电阻电平将其电阻从设定状态改变为复位状态。 复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。 第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。 与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。 操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。 未重新设置的单元格不受影响。

    Systems for reverse bias trim operations in non-volatile memory
    4.
    发明授权
    Systems for reverse bias trim operations in non-volatile memory 有权
    用于非易失性存储器中的反向偏置调整操作的系统

    公开(公告)号：US07492630B2

    公开(公告)日：2009-02-17

    申请号：US11461431

    申请日：2006-07-31

    申请人： Roy E. Scheuerlein ,  Tanmay Kumar

    发明人： Roy E. Scheuerlein ,  Tanmay Kumar

    IPC分类号： G11C13/04

    CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C11/56 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/72

    摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

    摘要翻译： 公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。 包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平下将其电阻从第一电阻上的设定状态改变为复位状态。 复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。 第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。 与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。 操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。 未重新设置的单元格不受影响。

    SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY
    5.
    发明申请
    SYSTEMS FOR CONTROLLED PULSE OPERATIONS IN NON-VOLATILE MEMORY 有权
    在非易失性存储器中控制脉冲运行的系统

    公开(公告)号：US20080025077A1

    公开(公告)日：2008-01-31

    申请号：US11461399

    申请日：2006-07-31

    申请人： Roy E. Scheuerlein ,  Tanmay Kumar

    发明人： Roy E. Scheuerlein ,  Tanmay Kumar

    IPC分类号： G11C11/00

    CPC分类号： G11C5/145 ,  G11C5/02 ,  G11C8/08 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/72

    摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

    摘要翻译： 提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。 受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。 在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。 可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。 在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。 在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。 这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

    Transistor layout configuration for tight-pitched memory array lines
    6.
    发明授权
    Transistor layout configuration for tight-pitched memory array lines 有权
    紧凑型内存阵列线的晶体管布局配置

    公开(公告)号：US07177227B2

    公开(公告)日：2007-02-13

    申请号：US11420787

    申请日：2006-05-29

    申请人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。 在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

    Controlled pulse operations in non-volatile memory
    9.
    发明授权
    Controlled pulse operations in non-volatile memory 失效
    非易失性存储器中的受控脉冲操作

    公开(公告)号：US07522448B2

    公开(公告)日：2009-04-21

    申请号：US11461393

    申请日：2006-07-31

    申请人： Roy E. Scheuerlein ,  Tanmay Kumar

    发明人： Roy E. Scheuerlein ,  Tanmay Kumar

    IPC分类号： G11C11/00

    CPC分类号： G11C8/08 ,  G11C5/02 ,  G11C5/145 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/72

    摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

    摘要翻译： 提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。 受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。 在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。 可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。 在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。 在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。 这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

    Transistor layout configuration for tight-pitched memory array lines
    10.
    发明授权
    Transistor layout configuration for tight-pitched memory array lines 有权
    紧凑型内存阵列线的晶体管布局配置

    公开(公告)号：US07054219B1

    公开(公告)日：2006-05-30

    申请号：US11095905

    申请日：2005-03-31

    申请人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    发明人： Christopher J. Petti ,  Roy E. Scheuerlein ,  Tanmay Kumar ,  Abhijit Bandyopadhyay

    IPC分类号： G11C8/00

    CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C8/08 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10894 ,  H01L27/10897

    摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.

    摘要翻译： 多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。 在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。 垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。 每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管 线。