公开(公告)号：US5408147A

公开(公告)日：1995-04-18

申请号：US116920

申请日：1993-09-07

申请人： Roy L. Yarbrough ,  Jay R. Chapin

发明人： Roy L. Yarbrough ,  Jay R. Chapin

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/018521 ,  H03K19/018592

摘要： A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors. In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.

摘要翻译： 用于将由一个高电位电源轨提供的电路的逻辑信号转换成由两个高电位轨道的电位不相等的另一个高电位电源轨提供的电路的电路。 本发明的转换器用于从3V提供的电路到5V供电的电路的转换，反之亦然，而没有任何静态电流ICCt，而不管上电顺序如何。 通过将直接连接到第二高电位电力轨的第二级的所有晶体管与位于第一高电位电力轨电平的转换器的第一级的输出隔离来消除静态电流。 在本发明的优选实施例中，由第二高电位电源轨供电的第二级的晶体管是PMOS晶体管，并且通过一系列控制NMOS晶体管将那些PMOS晶体管连接到第一级来实现隔离。 以这种方式，PMOS晶体管在必要时将完全关闭，以避免由于两个高电位电源轨的电位差而产生的任何不期望的导通路径。

公开(公告)号：US5617048A

公开(公告)日：1997-04-01

申请号：US614911

申请日：1996-03-13

申请人： Michael G. Ward ,  Roy L. Yarbrough ,  Jay R. Chapin

发明人： Michael G. Ward ,  Roy L. Yarbrough ,  Jay R. Chapin

IPC分类号： H03K3/2893 ,  H03K17/22 ,  H03K3/037

CPC分类号： H03K3/2893 ,  H03K17/22

摘要： A power-up circuit with hysteretic characteristics for regulating the activation of one or more output buffers of an extended logic circuit. The hysteresis of the power-up circuit of the invention permits turn on of a switching transistor of the circuit at one threshold voltage level and maintains the active state of that switching transistor until a second lower threshold voltage level. The hysteresis is achieved by providing two separate and electrically isolated control paths that are connected to the control node of the switching transistor. The first control path includes a plurality of diode devices designed to regulate the power supply level required to turn on the switching transistor. The second control path also includes diode devices but in lesser numbers so that, once the switching transistor is turned on by the first control path, it remains on in spite of fluctuations at the power supply rail.

摘要翻译： 具有滞后特性的上电电路，用于调节扩展逻辑电路的一个或多个输出缓冲器的激活。 本发明的上电电路的滞后允许电路的开关晶体管在一个阈值电压电平下导通，并保持该开关晶体管的有效状态直到第二较低的阈值电压电平。 通过提供连接到开关晶体管的控制节点的两个分离的和电隔离的控制路径来实现滞后。 第一控制路径包括被设计成调节导通开关晶体管所需的电源电平的多个二极管器件。 第二控制路径还包括二极管器件，但是数量较少，使得一旦开关晶体管被第一控制路径导通，其仍然保持接通，尽管在电源轨道处有波动。

公开(公告)号：US07719026B2

公开(公告)日：2010-05-18

申请号：US12098546

申请日：2008-04-07

申请人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

发明人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

IPC分类号： H01L29/74

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

摘要翻译： 公开了一种保护性SCR集成电路器件，其构造在相邻的N阱和P阱上并且限定阳极和阴极。 除了阳极和阴极接触结构之外，该器件具有桥接N阱和P阱的n型堆叠（N + / ESD）结构，以及P型堆叠（P + / PLDD）结构 -好。 n型堆叠结构和p型堆叠结构的分离提供低触发电压，而不涉及任何外部电路或端子，与其他物理尺寸和处理参数一起提供相对较高的保持电压而不牺牲ESD保护 健壮性 在一个实施例中，触发电压可以为约8V，同时呈现保持电压，其可以由约5-7V的n型叠层的横向尺寸来控制。

公开(公告)号：US20080253046A1

公开(公告)日：2008-10-16

申请号：US12098546

申请日：2008-04-07

申请人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

发明人： Lifang Lou ,  Jay R. Chapin ,  Donna Robinson-Hahn

IPC分类号： H02H9/00 ,  H01L29/73

CPC分类号： H01L29/87 ,  H01L27/0262

摘要： A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

摘要翻译： 公开了一种保护性SCR集成电路器件，其构造在相邻的N阱和P阱上并且限定阳极和阴极。 除了阳极和阴极接触结构之外，该器件具有桥接N阱和P阱的n型堆叠（N + / ESD）结构，以及P型堆叠（P + / PLDD）结构 -好。 n型堆叠结构和p型堆叠结构的分离提供了低触发电压，其与其他物理尺寸和处理参数一起也提供相对较高的保持电压。 在一个实施例中，触发电压可以为约8V，同时呈现保持电压，其可以由约5-7V的n型叠层的横向尺寸来控制。

公开(公告)号：US07079369B2

公开(公告)日：2006-07-18

申请号：US10207625

申请日：2002-07-29

申请人： Ronald B. Hulfachor ,  Jay R. Chapin

发明人： Ronald B. Hulfachor ,  Jay R. Chapin

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An ESD protective triggering circuit for a triggering circuit for a solid state ESD protective device. The arrangement is to provide a controlled current to the protective device that triggers the device so that the device snaps-back and additionally the triggering device enables the parasitic transistor to participate in the draining of the ESD current. The triggering circuit also terminates the current to the protective device when the ESD voltage starts to fall. The triggering circuit can be used in any computer controlled electronics system.

公开(公告)号：US5418474A

公开(公告)日：1995-05-23

申请号：US126914

申请日：1993-09-24

申请人： Jeffrey B. Davis ,  Jay R. Chapin

发明人： Jeffrey B. Davis ,  Jay R. Chapin

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/0948 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor to the output of the translator circuit to act as an early pulldown on the output by using that NMOS transistor to control a PMOS transistor which is in turn used to control the pulldown transistor. A second NMOS transistor of the transient-eliminating circuit also acts to control the pulldown transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.

摘要翻译： 一种用于最小化通过缓冲电路的上拉和下拉晶体管的同时传导的瞬态消除电路。 在用于将由一个高电位电力轨提供的电路的逻辑信号转换成由两个高电位轨道的电位不相等的另一个高电位电力轨提供的电路的缓冲电路中，瞬态消除电路 以这样的方式耦合在输出级和输入级之间，使得转换器可以独立于上电顺序和没有任何静态电流ICCt而被使用。 瞬态消除电路通过延迟下拉晶体管的导通直到上拉晶体管完全截止来最小化通过转换器的上拉和下拉晶体管的同时导通。 这在本发明的优选实施例中通过将NMOS晶体管耦合到转换器电路的输出来实现，以通过使用该NMOS晶体管来控制PMOS晶体管，以在输出端上作为早期下拉，该PMOS晶体管又用于控制下拉 晶体管。 瞬态消除电路的第二NMOS晶体管还用于通过以第一NMOS晶体管的反向模式操作来控制下拉晶体管，以便确保当需要时NMOS晶体管完全截止。

公开(公告)号：US4845442A

公开(公告)日：1989-07-04

申请号：US206012

申请日：1988-06-13

申请人： Jay R. Chapin ,  Thomas M. Luich

发明人： Jay R. Chapin ,  Thomas M. Luich

IPC分类号： H03K17/0412 ,  H03K19/088

CPC分类号： H03K19/088 ,  H03K17/04126

摘要： According to the teachings of this invention, a novel sense amplifier is provided which includes a current steering transistor having its emitter connected to the collector of a current mirror transistor, its collector connected to the base of an output transistor, and its base driven by the input signal. With a low input signal, the emitter of the current steering transistor is pulled low, thereby pulling the base of the output transistor low. Conversely, when the input signal is high, and the current steering transistor ceases to operate in the active saturation mode and begins to operate in the inverse active saturation mode, thereby providing current from its base to its collector in order to turn on the output transistor.

摘要翻译： 根据本发明的教导，提供了一种新颖的读出放大器，其包括具有连接到电流镜晶体管的集电极的发射极的电流导引晶体管，其集电极连接到输出晶体管的基极，其基极由 输入信号。 利用低输入信号，电流转向晶体管的发射极被拉低，从而将输出晶体管的基极拉低。 相反，当输入信号为高电平，并且电流导引晶体管停止工作在有源饱和模式并开始工作在反向有效饱和模式时，从而从其基极向其集电极提供电流，以便导通输出晶体管 。