公开(公告)号：US08673722B2

公开(公告)日：2014-03-18

申请号：US13255443

申请日：2011-03-23

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

摘要翻译： 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分 沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力 。

公开(公告)号：US20130043515A1

公开(公告)日：2013-02-21

申请号：US13255443

申请日：2011-03-23

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Ai ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Ai ,  Xing Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

摘要翻译： 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底，源极/漏极，栅极介电层和栅极，其特征在于，L形复合隔离层，其包围与沟道相邻的源极/漏极的侧面的一部分 并且源/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的L形绝缘薄层和与源极和漏极直接接触的L形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力 。

公开(公告)号：US08450155B2

公开(公告)日：2013-05-28

申请号：US13131602

申请日：2011-04-01

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

IPC分类号： H01L21/332 ,  H01L21/335 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.

摘要翻译： 本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。 根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善 信道的载波移动性和设备的性能。 本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。 根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

公开(公告)号：US20120187495A1

公开(公告)日：2012-07-26

申请号：US13201618

申请日：2010-09-25

申请人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

发明人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.

摘要翻译： 本发明提供了一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层 并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。 根据制造半导体器件的方法，通过硅杂质的注入，可以通过栅极和漏极区域中的晶格失配有效地将适当的应力引入锗通道中，使得沟道中电子的迁移率增强 并提高了设备​​的性能。

公开(公告)号：US08541847B2

公开(公告)日：2013-09-24

申请号：US13201618

申请日：2010-09-25

申请人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

发明人： Xia An ,  Yue Guo ,  Quanxin Yun ,  Ru Huang ,  Xing Zhang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.

摘要翻译： 本发明提供一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层 并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。 根据制造半导体器件的方法，通过硅杂质的注入，可以通过源极和漏极区域中的晶格失配有效地将合适的应力引入锗通道中，使得通道中电子的迁移率增强 并提高了设备​​的性能。

公开(公告)号：US20120289004A1

公开(公告)日：2012-11-15

申请号：US13390755

申请日：2011-10-14

申请人： Ru Huang ,  Zhiqiang Li ,  Yue Guo ,  Xia An ,  Quanxin Yun ,  Yinglong Huang ,  Xing Zhang

发明人： Ru Huang ,  Zhiqiang Li ,  Yue Guo ,  Xia An ,  Quanxin Yun ,  Yinglong Huang ,  Xing Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/0895 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66643 ,  H01L29/78

摘要： The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device.

摘要翻译： 本发明公开了一种Ge系N型肖特基场效应晶体管的制造方法，涉及超大规模集成电路制造工艺。 本发明在衬底和金属源极/漏极之间形成薄的高K电介质层。 薄层一方面可能阻止金属的电子波函数在半导体禁带中引起MIGS界面态，另一方面可能会钝化Ge界面处的悬挂键。 同时，由于绝缘介电层具有非常薄的厚度，并且电子可以基本上自由地通过，所以源极和漏极的寄生电阻不会显着增加。 该方法可以削弱费米能级钉扎效应，使费米能级接近Ge导带的位置，降低电子势垒，从而提高Ge基肖特基晶体管的电流开关比，提高Ge NMOS器件。

公开(公告)号：US20120032239A1

公开(公告)日：2012-02-09

申请号：US13131602

申请日：2011-04-01

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Xing Zhang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.

摘要翻译： 本发明涉及CMOS超大规模集成电路，并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。 根据本发明，应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间，并且通过直接接触衬底的应变介电层在沟道中诱发应变，从而改善 信道的载波移动性和设备的性能。 本发明的具体效果包括：通过使用具有拉伸应变的应变电介质层，可以在沟道中诱发拉伸应变，以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变，以增加通道的空穴迁移率。 根据本发明，不仅引入通道应力的有效性，而且基本上也提高了场效应晶体管的器件结构，从而增加了抑制器件的短沟道效应的能力。

公开(公告)号：US08288238B2

公开(公告)日：2012-10-16

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点

公开(公告)号：US20120115297A1

公开(公告)日：2012-05-10

申请号：US13133643

申请日：2010-09-25

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Chunhui Fan ,  Shuangshuang Pu ,  Runsheng Wang ,  Quanxin Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching. Therefore, a planar TFET may be fabricated self-alignedly based on this process, thereby the rigid requirements on the alignment deviation of the photolithography during the fabrication procedure of a planar TFET is alleviated, which facilitates to fabricate a planar TFET device with stable and reliable characteristics.

摘要翻译： 本发明公开了一种基于平面工艺自对准地制造隧道场效应晶体管（TFET）的方法，从而降低了用于制造平面TFET的光刻工艺的要求。 在该方法中，TFET的源极区域和漏极区域不直接由光刻法定义; 相反，它们由位于栅极的有源区域和两侧上并且不同于限定沟道区域的电介质膜的另一介电膜限定。 通过用蚀刻选择性地去除源极和漏极区域上的电介质膜，可以消除用于限定沟道区域，源极和漏极区域的三次光刻处理之间由于取向偏差引起的影响。 因此，可以基于该工艺自平面地制造平面TFET，从而减轻了在平面TFET的制造过程期间对光刻的对准偏差的刚性要求，这有助于制造具有稳定和可靠的平面TFET器件 特点