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1.发明申请Unified instruction pipeline for power reduction in a digital signal processor integrated circuit 有权用于数字信号处理器集成电路中的功率降低的统一指令流水线公开(公告)号：US20050076194A1
公开(公告)日：2005-04-07
申请号：US10651234
申请日：2003-08-28
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.
摘要翻译： 用于降低数字特定信号处理器集成电路中的功耗的方法和装置。 数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。 全局内存集群到内存集群中。 具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。 非活动数据总线通过使用总线状态保持器保持其状态。 循环缓冲器在程序循环中存储指令以避免存储器访问。 功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。 本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。
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公开(公告)号：US20050146910A1
公开(公告)日：2005-07-07
申请号：US11040954
申请日：2005-01-21
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
摘要翻译： 集成电路中的可重构存储器包括存储器单元阵列和存储器控制器。 测试可重配置存储器中的存储器单元阵列以确定它们是否不可用，如果是，则它们的相关物理地址对应于它们的物理位置。 在确定存在任何故障的物理地址之后，映射与不可用存储器单元或存储器块的物理位置相关联的物理地址位置，以避免对其进行寻址。 当映射不可用的存储器位置或存储器块减少总容量时，可重构存储器具有足够的容量以使集成电路保持功能可用。
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公开(公告)号：US20060010335A1
公开(公告)日：2006-01-12
申请号：US11219008
申请日：2005-09-01
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
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4.发明申请Tables with direct memory access descriptor lists for distributed direct memory access 失效具有用于分布式直接内存访问的直接内存访问描述符列表公开(公告)号：US20050216613A1
公开(公告)日：2005-09-29
申请号：US11036827
申请日：2005-01-14
申请人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle Philhower , Ruchir Shah
发明人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle Philhower , Ruchir Shah
IPC分类号： G06F13/28
CPC分类号： H04L49/90 , G06F12/08 , G06F13/28 , G06F2213/0038 , G11C7/1072
摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.
摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，就可以建立与全局缓冲存储器的DMA程序。
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公开(公告)号：US20050125572A1
公开(公告)日：2005-06-09
申请号：US11036828
申请日：2005-01-14
申请人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle Philhower , Ruchir Shah
发明人： Kumar Ganapathy , Ruban Kanapathippillai , Saurin Shah , George Moussa , Earle Philhower , Ruchir Shah
IPC分类号： G06F13/28
CPC分类号： H04L49/90 , G06F12/08 , G06F13/28 , G06F2213/0038 , G11C7/1072
摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.
摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，就可以建立与全局缓冲存储器的DMA程序。
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