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1.发明申请Unified instruction pipeline for power reduction in a digital signal processor integrated circuit 有权用于数字信号处理器集成电路中的功率降低的统一指令流水线公开(公告)号：US20050076194A1
公开(公告)日：2005-04-07
申请号：US10651234
申请日：2003-08-28
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle Philhower , Manoj Mehta , Kenneth Malich
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.
摘要翻译： 用于降低数字特定信号处理器集成电路中的功耗的方法和装置。 数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。 全局内存集群到内存集群中。 具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。 非活动数据总线通过使用总线状态保持器保持其状态。 循环缓冲器在程序循环中存储指令以避免存储器访问。 功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。 本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。
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公开(公告)号：US07233166B2
公开(公告)日：2007-06-19
申请号：US10649067
申请日：2003-08-27
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： H03K19/003 , H03K17/16 , G11C27/02
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.
摘要翻译： 总线状态保持者保持不活动的公共汽车的稳定状态以节省电力。 在本发明的一个实施例中，总线状态保持器包括多个复用器和多个触发器。 多个触发器响应于选择信号来存储总线的状态。
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3.发明授权IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic 有权具有控制器的IC存储器复合器用于存储器块的集群使用套环逻辑进行I / O复用公开(公告)号：US07318115B2
公开(公告)日：2008-01-08
申请号：US10649090
申请日：2003-08-27
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.
摘要翻译： 用于降低数字特定信号处理器集成电路中的功耗的方法和装置。 数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。 全局内存集群到内存集群中。 具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。 非活动数据总线通过使用总线状态保持器保持其状态。 循环缓冲器在程序循环中存储指令以避免存储器访问。 功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。 本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。
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4.发明授权Unified shared pipeline allowing deactivation of RISC/DSP units for power saving 有权统一的共享管道允许停用RISC / DSP单元以节省能耗公开(公告)号：US07287148B2
公开(公告)日：2007-10-23
申请号：US10651234
申请日：2003-08-28
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F15/16
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.
摘要翻译： 一种集成电路，包括执行RISC指令的简化指令集计算机（RISC）控制器，用于执行DSP指令的一个或多个数字信号处理（DSP）单元，以及耦合到所述RISC控制器和所述一个或多个DSP单元的统一指令流水线 统一指令流水线，用于解码和启动统一RISC和DSP指令集的RISC指令和DSP指令的执行，当DSP指令不活动时，统一指令流水线解码并启动RISC指令，并解码并启动 当RISC指令不活动时，DSP指令。
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5.发明授权Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus 有权选择性地将存储器耦合全局总线数据位复合到较窄的功能单元耦合本地总线公开(公告)号：US06732203B2
公开(公告)日：2004-05-04
申请号：US10109826
申请日：2002-03-29
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F1338
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.
摘要翻译： 在一个实施例中，总线复用器位于集成电路的存储器和功能单元之间。 总线多路复用器的输入耦合到具有位宽度的全局总线。 具有较小位宽度的本地总线耦合到总线复用器的输出。 总线复用器有选择地将全局总线上的数据位复用到本地总线的位上。 在另一实施例中，集成电路包括存储器，全局总线和耦合在一起的功能单元。 功能单元包括具有耦合到全局总线的输入的总线复用器和耦合到总线多路复用器的输出的本地总线。 本地总线的总线宽度小于全球总线的总线宽度。 总线复用器从全局总线的位的子集中选择数据以耦合到本地总线的位上。
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公开(公告)号：US20060010335A1
公开(公告)日：2006-01-12
申请号：US11219008
申请日：2005-09-01
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
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公开(公告)号：US20050146910A1
公开(公告)日：2005-07-07
申请号：US11040954
申请日：2005-01-21
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
摘要翻译： 集成电路中的可重构存储器包括存储器单元阵列和存储器控制器。 测试可重配置存储器中的存储器单元阵列以确定它们是否不可用，如果是，则它们的相关物理地址对应于它们的物理位置。 在确定存在任何故障的物理地址之后，映射与不可用存储器单元或存储器块的物理位置相关联的物理地址位置，以避免对其进行寻址。 当映射不可用的存储器位置或存储器块减少总容量时，可重构存储器具有足够的容量以使集成电路保持功能可用。
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公开(公告)号：US07502977B2
公开(公告)日：2009-03-10
申请号：US11040954
申请日：2005-01-21
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
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公开(公告)号：US07111190B2
公开(公告)日：2006-09-19
申请号：US10056393
申请日：2002-01-24
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
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公开(公告)号：US07490260B2
公开(公告)日：2009-02-10
申请号：US11219008
申请日：2005-09-01
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G11C29/88 , G11C29/883
摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.
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