公开(公告)号：US06324181B1

公开(公告)日：2001-11-27

申请号：US09062158

申请日：1998-04-16

申请人： Don Yih Wong ,  David A. Kranzler ,  Ruchi Wadhawan ,  Craig Owens

发明人： Don Yih Wong ,  David A. Kranzler ,  Ruchi Wadhawan ,  Craig Owens

IPC分类号： H04J302

CPC分类号： H04L12/4637

摘要： In a fibre channel network environment wherein an arbitrated loop is provided a switchable connection with another arbitrated loop, a technique and corresponding apparatus are provided for controlling signal paths through the hubs stack between any two devices such that routing of a signal and interactive communication can be carried out transparently to the fibre channel network without excessive overhead, and wherein control is changed in an orderly manner such that end-to-end device connections are unaware that they are not connected to the same hub. A switched arbitrated loop (SAL) according to the invention provides the concurrent bandwidth resource of a fabric switch without the extra features which would increase design cost and operational overhead. In a specific embodiment, a switched arbitrated loop supports only 126 nodes for stations (plus one fabric port) in a single loop topology. The invention provides the concurrent connections and high bandwidth capabilities of a conventional fabric switch, but at a cost close to that of a conventional hub while behaving such that devices connected to it are unaware that they are not on a normal loop when they are communicating.

摘要翻译： 在其中向仲裁环路提供与另一个仲裁环路的可切换连接的光纤通道网络环境中，提供了一种技术和相应的装置，用于控制通过任何两个设备之间的集线器堆叠的信号路径，使得信号和交互式通信的路由可以是 对光纤通道网络透明地执行，而不会有过多的开销，并且其中控制以有序的方式改变，使得端到端设备连接不知道它们没有连接到同一集线器。 根据本发明的交换仲裁环路（SAL）提供了结构交换机的并发带宽资源，而没有增加设计成本和操作开销的额外特征。 在具体实施例中，交换仲裁环路在单个环路拓扑中仅支持126个节点（加上一个结构端口）。 本发明提供了传统结构交换机的并发连接和高带宽能力，但成本接近常规集线器的成本，同时使得连接到它的设备不知道当它们正在通信时它们不在正常环路上。

公开(公告)号：US5715287A

公开(公告)日：1998-02-03

申请号：US544745

申请日：1995-10-18

申请人： Ruchi Wadhawan ,  Craig Owens

发明人： Ruchi Wadhawan ,  Craig Owens

IPC分类号： H04L12/413 ,  H04L29/08 ,  H04L23/00

CPC分类号： H04L12/40136 ,  H04L69/323 ,  Y02B60/31

摘要： A method and apparatus is provided allowing a dual-speed network adapter to connect to the same physical connector without the use of mechanical or electro-mechanical switches. On the transmit path, the invention uses a differential amplifier buffer (130) to selectively couple a high speed transmit paths to the network, with the differential amplifier connected to the same output impedance as one of the two driver circuits. On the receive path, the invention allows data to be received in parallel by two receiver circuits, with one circuit isolated from the other with a pair of very high input impedance emitter/followers (40, 50).

摘要翻译： 提供了一种方法和装置，允许双速网络适配器在不使用机械或机电开关的情况下连接到同一物理连接器。 在发送路径上，本发明使用差分放大器缓冲器（130）来选择性地将高速发送路径耦合到网络，差分放大器连接到与两个驱动器电路中的一个相同的输出阻抗。 在接收路径上，本发明允许由两个接收机电路并行地接收数据，其中一个电路与一对非常高的输入阻抗发射器/跟随器（40,50）隔离。

公开(公告)号：US20120233360A1

公开(公告)日：2012-09-13

申请号：US13474373

申请日：2012-05-17

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US08176257B2

公开(公告)日：2012-05-08

申请号：US13087974

申请日：2011-04-15

申请人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

发明人： Ruchi Wadhawan ,  Jason M. Kassoff ,  George Kong Yiu

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/0835 ,  G06F12/12

摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

摘要翻译： 在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

公开(公告)号：US07970970B2

公开(公告)日：2011-06-28

申请号：US12787865

申请日：2010-05-26

申请人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

发明人： Sridhar P. Subramanian ,  James B. Keller ,  Ruchi Wadhawan ,  George Kong Yiu ,  Ramesh Gunna

IPC分类号： G06F13/00

CPC分类号： G06F13/362 ,  G06F13/4022

摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

摘要翻译： 在一个实施例中，开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。 在另一个实施例中，预期了一种方法。

公开(公告)号：US07680963B2

公开(公告)日：2010-03-16

申请号：US11682065

申请日：2007-03-05

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US07349399B1

公开(公告)日：2008-03-25

申请号：US10327555

申请日：2002-12-20

申请人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

发明人： Edmund G. Chen ,  John G. Favor ,  Ruchi Wadhawan ,  Gregory G. Minshall

IPC分类号： H04L12/56 ,  H04L12/54 ,  G06F9/44

CPC分类号： H04L49/9094 ,  H04L49/90

摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.

摘要翻译： 将参照具体实施方式和附图更好地描述本发明的这些和其它方面。 描述了使用链表对包进行无序处理的方法和装置。 在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。 该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。 该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于 全球秩序。 该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

公开(公告)号：US07269682B2

公开(公告)日：2007-09-11

申请号：US11201573

申请日：2005-08-11

申请人： Sridhar P. Subramanian ,  James B. Keller ,  George Kong Yiu ,  Ruchi Wadhawan

发明人： Sridhar P. Subramanian ,  James B. Keller ,  George Kong Yiu ,  Ruchi Wadhawan

IPC分类号： G06F13/00 ,  G06F13/36 ,  H04L12/00 ,  H04L12/12

CPC分类号： G06F13/364 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

摘要翻译： 在各种实施例中，装置包括多个代理和互连。 在一个实施方案中，多种试剂包括第一至第四试剂。 互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中，每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

公开(公告)号：US20070038796A1

公开(公告)日：2007-02-15

申请号：US11201573

申请日：2005-08-11

申请人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

发明人： Sridhar Subramanian ,  James Keller ,  George Yiu ,  Ruchi Wadhawan

IPC分类号： G06F13/00

CPC分类号： G06F13/364 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

摘要翻译： 在各种实施例中，装置包括多个代理和互连。 在一个实施方案中，多种试剂包括第一至第四试剂。 互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中，每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

公开(公告)号：US5793260A

公开(公告)日：1998-08-11

申请号：US641101

申请日：1996-04-26

申请人： Marwan A. Fawal ,  Burton B. Lo ,  Ruchi Wadhawan

发明人： Marwan A. Fawal ,  Burton B. Lo ,  Ruchi Wadhawan

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K3/0231 ,  H01G9/048 ,  H03L7/085

CPC分类号： H03K3/0231

摘要： A current-controlled oscillator with first and second differential comparators (640, 840) serving as inputs, first and second voltage independent multi-layered integrated capacitors (600, 800) corresponding to the first and second comparators (640, 840), and a RS latch (700) for switching operation between the two comparators (640, 840) thereby achieving oscillation. The multi-layered integrated capacitors (600, 800) are designed to provide voltage independent capacitance.

摘要翻译： 具有用作输入的第一和第二差分比较器（640,840）的电流控制振荡器，对应于第一和第二比较器（640,840）的第一和第二电压无关多层集成电容器（600,800），以及 RS锁存器（700），用于在两个比较器（640,840）之间切换操作，从而实现振荡。 多层集成电容器（600,800）被设计成提供电压独立的电容。