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59 条记录 (耗时 0.033 秒)

    Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
    1.
    发明授权
    Integrated circuit power management for reducing leakage current in circuit arrays and method therefor 有权
    集成电路电源管理，用于减少电路阵列中的漏电流及其方法

    公开(公告)号：US06917555B2

    公开(公告)日：2005-07-12

    申请号：US10675005

    申请日：2003-09-30

    申请人： Ryan D. Bedwell ,  Christopher K. Y. Chun ,  Qadeer A. Qureshi ,  John J. Vaglica

    发明人： Ryan D. Bedwell ,  Christopher K. Y. Chun ,  Qadeer A. Qureshi ,  John J. Vaglica

    IPC分类号： G06F1/32 ,  G11C5/14 ,  G11C7/22 ,  G11C7/00

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C5/14 ,  G11C7/22 ,  G11C2207/2227 ,  Y02D10/14

    摘要： Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

    摘要翻译： 在具有与存储器阵列接口的处理器的处理系统的低功率模式期间，在存储器阵列中消除泄漏电流。 因为创建了两个电源平面，所以处理器可以在阵列掉电时绕过存储器阵列，继续执行使用系统存储器的指令。 开关选择性地去除与电源电压端子的电连接，以响应于执行指令或源自系统处于不同于处理器的系统的来源的处理器启动的控制。 在恢复对存储器阵列的电力的情况下，取决于支持阵列到存储器阵列的两个电力平面中的哪一个位于何处，数据可能也可能不需要被标记为不可用。 可以使用预定的标准来控制恢复电力的时间。 可以实现多个阵列以独立地减少泄漏电流。

    State retention power gating latch circuit
    6.
    发明授权
    State retention power gating latch circuit 有权
    状态保持电源门控锁存电路

    公开(公告)号：US07164301B2

    公开(公告)日：2007-01-16

    申请号：US11125462

    申请日：2005-05-10

    申请人： Christopher K. Y. Chun

    发明人： Christopher K. Y. Chun

    IPC分类号： H03K3/289 ,  H03K3/356

    CPC分类号： H03K3/356008 ,  H03K3/012

    摘要： A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.

    摘要翻译： 一种锁存电源的方法，包括检测锁存器的状态，检测功率门信号，在功率门信号被否定时为锁存器供电，以及当功率门信号被断言时从锁存器去除功率，并且锁存器 处于预定状态。 该方法可以包括以下任何一个或多个：将锁存器的节点拉至选定状态，同时确定电源门信号以确保锁存器在预定状态下上电，提供指示锁存状态的信号和电源门 信号到具有指示输出的逻辑门的相应输入，基于逻辑门的输出状态将电源电压切换到锁存器的电源输入，并且闭合开关以将锁存器的节点拉低。

    Semiconductor to optical link
    8.
    发明授权
    Semiconductor to optical link 失效
    半导体到光链路

    公开(公告)号：US5959315A

    公开(公告)日：1999-09-28

    申请号：US844027

    申请日：1992-03-02

    申请人： Michael S. Lebby ,  Christopher K. Y. Chun

    发明人： Michael S. Lebby ,  Christopher K. Y. Chun

    IPC分类号： G02B6/42 ,  H01L33/00

    CPC分类号： G02B6/4239 ,  G02B6/4202 ,  G02B6/4249

    摘要： One surface of a semiconductor component attached to one surface of a header with an opposite surface of the component having an optical input/output positioned adjacent one end of an optical fiber. The component and optical fiber are fixedly attached with no strain by a curable gel with the header acting as a heat sink. Electrical contacts are made to the component by means of leads formed on the header and/or a conductive coating deposited on the optical fiber.

    摘要翻译： 半导体部件的一个表面附接到集管的一个表面，其中部件的相对表面具有邻近光纤的一端定位的光学输入/输出。 组件和光纤通过可固化凝胶固定地附着，其中头部用作散热器。 通过形成在集管上的引线和/或沉积在光纤上的导电涂层，对部件进行电接触。

    Signal processing method
    9.
    发明授权
    Signal processing method 失效
    信号处理方法

    公开(公告)号：US5703506A

    公开(公告)日：1997-12-30

    申请号：US578726

    申请日：1995-12-26

    申请人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    发明人： Stephen G. Shook ,  Christopher K. Y. Chun ,  Daniel B. Schwartz

    IPC分类号： H04B10/158 ,  H04L25/06 ,  H04Q9/00 ,  G08G1/01

    CPC分类号： H04B10/697 ,  H04L25/062

    摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.

    摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。

    Method for making optical interface unit with detachable photonic device
    10.
    发明授权
    Method for making optical interface unit with detachable photonic device 失效
    用可拆卸光子器件制造光接口单元的方法

    公开(公告)号：US5522002A

    公开(公告)日：1996-05-28

    申请号：US370692

    申请日：1995-01-10

    申请人： Christopher K. Y. Chun ,  Shun-Meen Kuo ,  Gary F. Witting

    发明人： Christopher K. Y. Chun ,  Shun-Meen Kuo ,  Gary F. Witting

    IPC分类号： G02B6/42

    CPC分类号： G02B6/4292 ,  G02B6/4249 ,  G02B6/4246

    摘要： A substrate having a photonic device mounted thereon with a working portion that is operably connected to at least one electrical lead. A molded optical portion having a surface for light signal to enter and to exit is formed that encapsulates the substrate, the photonic device, and a portion of the first and second electrical lead. An optical connector is formed to plug into the molded optical portion to connect a fiber bundle thereto and the optical portion is electrically connected to an interconnect module.

    摘要翻译： 一种具有安装在其上的光子器件的衬底，其具有可操作地连接到至少一个电引线的工作部分。 形成具有用于光信号进入和退出的表面的模制光学部分，其封装基板，光子器件以及第一和第二电引线的一部分。 光连接器被形成为插入到模制的光学部分中以将光纤束连接到其上，并且光学部分电连接到互连模块。