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公开(公告)号：US06954100B2
公开(公告)日：2005-10-11
申请号：US10660847
申请日：2003-09-12
CPC分类号： H03K3/356113
摘要： A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.
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公开(公告)号：US07365596B2
公开(公告)日：2008-04-29
申请号：US10819383
申请日：2004-04-06
IPC分类号： G05F1/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/4072 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.
摘要翻译： 通过使用从电路块或电路块的一部分去除功率的功率门控，可以降低功耗，以减少漏电流。 一个实施例使用修改的状态保持触发器，其能够在电力被去除或部分地从电路中移除时保持状态。 另一实施例使用修改状态保持缓冲器，其能够在电力被去除或部分地从电路中移除时保持状态。 状态保持触发器和缓冲器可以用于允许状态保持同时仍然减少漏电流。 还公开了使用例如状态保持触发器和缓冲器来降低功率和保持状态的各种方法。 例如，软件，硬件或软件和硬件方法的组合可以用于在保持状态的同时进入深度睡眠或空闲模式。
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公开(公告)号：US07164301B2
公开(公告)日：2007-01-16
申请号：US11125462
申请日：2005-05-10
CPC分类号： H03K3/356008 , H03K3/012
摘要： A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.
摘要翻译： 一种锁存电源的方法，包括检测锁存器的状态，检测功率门信号，在功率门信号被否定时为锁存器供电，以及当功率门信号被断言时从锁存器去除功率，并且锁存器 处于预定状态。 该方法可以包括以下任何一个或多个：将锁存器的节点拉至选定状态，同时确定电源门信号以确保锁存器在预定状态下上电，提供指示锁存状态的信号和电源门 信号到具有指示输出的逻辑门的相应输入，基于逻辑门的输出状态将电源电压切换到锁存器的电源输入，并且闭合开关以将锁存器的节点拉低。
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公开(公告)号：US5959315A
公开(公告)日：1999-09-28
申请号：US844027
申请日：1992-03-02
CPC分类号： G02B6/4239 , G02B6/4202 , G02B6/4249
摘要： One surface of a semiconductor component attached to one surface of a header with an opposite surface of the component having an optical input/output positioned adjacent one end of an optical fiber. The component and optical fiber are fixedly attached with no strain by a curable gel with the header acting as a heat sink. Electrical contacts are made to the component by means of leads formed on the header and/or a conductive coating deposited on the optical fiber.
摘要翻译： 半导体部件的一个表面附接到集管的一个表面，其中部件的相对表面具有邻近光纤的一端定位的光学输入/输出。 组件和光纤通过可固化凝胶固定地附着，其中头部用作散热器。 通过形成在集管上的引线和/或沉积在光纤上的导电涂层，对部件进行电接触。
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公开(公告)号：US5703506A
公开(公告)日：1997-12-30
申请号：US578726
申请日：1995-12-26
IPC分类号： H04B10/158 , H04L25/06 , H04Q9/00 , G08G1/01
CPC分类号： H04B10/697 , H04L25/062
摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.
摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。
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6.发明授权
公开(公告)号：US5522002A
公开(公告)日：1996-05-28
申请号：US370692
申请日：1995-01-10
IPC分类号： G02B6/42
CPC分类号： G02B6/4292 , G02B6/4249 , G02B6/4246
摘要： A substrate having a photonic device mounted thereon with a working portion that is operably connected to at least one electrical lead. A molded optical portion having a surface for light signal to enter and to exit is formed that encapsulates the substrate, the photonic device, and a portion of the first and second electrical lead. An optical connector is formed to plug into the molded optical portion to connect a fiber bundle thereto and the optical portion is electrically connected to an interconnect module.
摘要翻译： 一种具有安装在其上的光子器件的衬底，其具有可操作地连接到至少一个电引线的工作部分。 形成具有用于光信号进入和退出的表面的模制光学部分，其封装基板，光子器件以及第一和第二电引线的一部分。 光连接器被形成为插入到模制的光学部分中以将光纤束连接到其上，并且光学部分电连接到互连模块。
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公开(公告)号：US5521992A
公开(公告)日：1996-05-28
申请号：US283349
申请日：1994-08-01
CPC分类号： G02B6/43 , G02B6/1221 , H01L2224/16225 , H01S5/02248
摘要： A molded optical interconnect is provided. A plurality of electrical tracings is disposed thereon. An optical module having an optical surface and a photonic device are operably coupled to an interconnect substrate. A molded optical portion having a core region with a first end and a cladding region is positioned with the first end of the core region being adjacent to the optical surface of the integrated circuit to operably couple the first end of the core region to the optical surface of the integrated circuit.
摘要翻译： 提供了一种模制的光学互连。 多个电追踪被放置在其上。 具有光学表面和光子器件的光学模块可操作地耦合到互连衬底。 具有芯区域的模制光学部分具有第一端和包层区域，其中芯区域的第一端与集成电路的光学表面相邻，以将芯区域的第一端可操作地耦合到光学表面 的集成电路。
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公开(公告)号：US5304949A
公开(公告)日：1994-04-19
申请号：US989671
申请日：1992-12-14
摘要： A common base amplifier (29) has an input (31) and an output (32). A transistor (33) has an emitter coupled to the input (31) of the amplifier (29), a collector coupled to the output (32) of the amplifier (29), and a base coupled to a voltage reference (34) provides low input impedance and unity current gain. A control circuit (38) controls a first bias circuit (36) and a second bias circuit (37). The second bias circuit (37) is coupled to the collector of the transistor (33) and provides a bias current for the transistor (33) while transistor (33) outputs the bias current which is received by the first bias circuit (36). Control circuit (38) determines the current magnitude for both the first bias circuit (36) and the second bias circuit (37) and ensures that the current magnitudes are maintained at a fixed ratio.
摘要翻译： 公共基极放大器（29）具有输入端（31）和输出端（32）。 晶体管（33）具有耦合到放大器（29）的输入（31）的发射极，耦合到放大器（29）的输出（32）的集电极，耦合到电压基准（34）的基极提供 低输入阻抗和单位电流增益。 控制电路（38）控制第一偏置电路（36）和第二偏置电路（37）。 第二偏置电路（37）耦合到晶体管（33）的集电极，并为晶体管（33）提供偏置电流，同时晶体管（33）输出由第一偏置电路（36）接收的偏置电流。 控制电路（38）确定第一偏置电路（36）和第二偏置电路（37）两者的电流幅值，并确保电流幅值保持在固定比例。
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公开(公告)号：US5265184A
公开(公告)日：1993-11-23
申请号：US889335
申请日：1992-05-28
CPC分类号： G02B6/30 , G02B6/1221 , G02B6/13 , G02B6/424 , G02B6/4255
摘要： A method for manufacturing a molded waveguide (50) is provided. A first cladding layer (20) is provided. Channels (21) are formed in the first cladding layer (20). A second cladding layer (40) is subsequently provided. The channels (21) in the first cladding layer (20) are then filled with an optically transparent polymer. The second cladding layer (40) is subsequently affixed over the channels (21) of the first cladding layer (20), thereby enclosing the channels (21).
摘要翻译： 提供了一种制造模制波导（50）的方法。 提供第一覆层（20）。 通道（21）形成在第一覆层（20）中。 随后提供第二包层（40）。 然后用光学透明的聚合物填充第一包层（20）中的通道（21）。 随后，第二包层（40）固定在第一包层（20）的通道（21）上，从而封闭通道（21）。
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公开(公告)号：US5703504A
公开(公告)日：1997-12-30
申请号：US578727
申请日：1995-12-26
CPC分类号： H03F3/08 , H03F3/3432 , H03F3/45982 , H03G3/345
摘要： A signal processing circuit (10) generates a bias signal (27) that is used for biasing a comparator (26). An input signal (14) is compared to the bias signal (27) in order to reconstruct the input signal (14) on an output of the comparator. The bias signal (27) is generated by selecting the larger of a percent of the input signal (23) or an offset signal (24) that is larger than a minimum value of the input signal.
摘要翻译： 信号处理电路（10）产生用于偏置比较器（26）的偏置信号（27）。 将输入信号（14）与偏置信号（27）进行比较，以便重建比较器的输出端上的输入信号（14）。 偏置信号（27）通过选择输入信号（23）的百分比中的较大者或大于输入信号的最小值的偏移信号（24）来产生。
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