公开(公告)号：US06275428B1

公开(公告)日：2001-08-14

申请号：US09598209

申请日：2000-06-21

申请人： Ryo Fukuda ,  Osamu Wada ,  Shinji Miyano

发明人： Ryo Fukuda ,  Osamu Wada ,  Shinji Miyano

IPC分类号： G11C700

CPC分类号： G11C29/14 ,  G11C29/48 ,  G11C2207/104

摘要： There is provided a memory-embedded semiconductor integrated circuit device capable of being tested in a shorter test time. The memory-embedded semiconductor integrated circuit device includes: a logic part provided on a semiconductor substrate; a memory macro provided on the semiconductor substrate to be consolidated with the logic part; a test input terminal for inputting a test input signal; a test circuit including a test signal generator for generating an output switching signal and a test signal, which serves to carry out a test operation of the memory macro, on the basis of the test input signal, and a switching circuit for selectively outputting one of an output of the memory macro, which has been test-operated by the test signal, and the test input signal in accordance with the output switching signal; and a test output terminal for receiving an output of the switching circuit to output the output of the switching circuit to the outside.

摘要翻译： 提供了一种能够在较短测试时间内测试的内存嵌入式半导体集成电路器件。 存储器嵌入式半导体集成电路器件包括：设置在半导体衬底上的逻辑部分; 提供在半导体衬底上以与逻辑部分合并的存储器宏; 用于输入测试输入信号的测试输入端; 测试电路，包括用于产生输出切换信号的测试信号发生器和用于基于测试输入信号执行存储器宏的测试操作的测试信号;以及切换电路，用于选择性地输出 已经由测试信号测试的存储器宏的输出和根据输出切换信号的测试输入信号; 以及测试输出端子，用于接收开关电路的输出，以将开关电路的输出输出到外部。

公开(公告)号：US06601199B1

公开(公告)日：2003-07-29

申请号：US09405128

申请日：1999-09-24

申请人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

发明人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

IPC分类号： G01R3128

CPC分类号： G01R31/3167 ,  G01R31/318505 ,  Y10S257/909

摘要： A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

摘要翻译： 多个存储器宏布置在半导体芯片中。 宏ID生成电路生成用于识别存储宏的宏ID，并具有不同的布局。 这些宏ID生成电路被布置在半导体芯片中的存储器宏之外，使得存储器宏中的测试控制块可以在所有存储器宏之间使用相同的布局来减少设计负载。

公开(公告)号：US06429521B1

公开(公告)日：2002-08-06

申请号：US09531177

申请日：2000-03-21

申请人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

发明人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L27/118 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

摘要翻译： 在半导体基板上，形成有由金属布线层（例如铝布线）形成的具有三层布线层的第一宏观单元和具有由金属布线形成的三层布线层的第二宏观单元 层与第一个宏单元类似。 第一宏单元形成为具有三个布线层的布线结构，尽管最初所需数量的金属布线层是两个。 第一宏单元上的各层的金属布线层由与第二宏单元上的各层的金属布线层相同的材料形成。 此外，各层的金属布线层形成为具有相同的膜厚度。 为了将第一和第二宏单元彼此连接，形成宏布线布置在第三布线层（最上布线层）中。

公开(公告)号：US6066896A

公开(公告)日：2000-05-23

申请号：US551

申请日：1997-12-30

申请人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

发明人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L27/118 ,  H01L2924/0002 ,  Y10S257/903

摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

公开(公告)号：US06744680B2

公开(公告)日：2004-06-01

申请号：US10342248

申请日：2003-01-15

申请人： Toshimasa Namekawa ,  Shinji Miyano ,  Atsushi Suzuki

发明人： Toshimasa Namekawa ,  Shinji Miyano ,  Atsushi Suzuki

IPC分类号： G11C700

CPC分类号： H01L27/10897 ,  H01L27/0218

摘要： A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

摘要翻译： 半导体衬底具有形成在掩埋绝缘膜上或在空腔区域上的体区域和半导体区域。 体区域包含多个存储单元，读出放大器和列选择栅极，而半导体区域包含字线选择电路和列选择电路。

公开(公告)号：US5754481A

公开(公告)日：1998-05-19

申请号：US857559

申请日：1997-05-16

申请人： Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

发明人： Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

IPC分类号： G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078

摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.

摘要翻译： 半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。 存储单元阵列具有以阵列形式排列的动态存储单元。 行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。 每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。 读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。 读出放大器控制电路控制读出放大器的工作。 数据锁存器锁存读出数据和写入数据。 传输门在数据锁存器和读出放大器之间传送数据。 传输门控制电路控制传输门。 写入电路与时钟信号同步地将数据写入数据锁存器。 在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后 数据锁存器，读出放大器控制电路激活读出放大器。

公开(公告)号：US5698876A

公开(公告)日：1997-12-16

申请号：US576477

申请日：1995-12-21

申请人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

发明人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC分类号： G11C11/401 ,  G11C11/00 ,  G11C11/4074 ,  G11C29/14 ,  H01L21/82 ,  H01L27/02 ,  H01L27/10 ,  H01L27/118 ,  H01L27/108

CPC分类号： G11C29/14 ,  G11C11/005 ,  G11C11/4074 ,  H01L27/0207 ,  Y10S257/909

摘要： A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

摘要翻译： 可以在短时间内设计存储器 - 宏型半导体器件以具有不占用大面积的期望的存储容量，从而降低芯片成本。 半导体器件包括具有子存储器宏的存储器宏，每个子存储器宏具有DRAM存储单元阵列，以及用于从阵列的存储器单元中选择任何所需存储单元的行解码器和列解码器。 存储器宏还包括具有DC电位产生电路的控制部分宏，用于产生驱动子存储器宏所需的各种DC电位。 子存储器宏中的至少一个与控制部分宏组合以形成作为能够存储N位的整数倍的单片存储器的存储器宏。

公开(公告)号：US5640365A

公开(公告)日：1997-06-17

申请号：US524630

申请日：1995-09-07

申请人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

发明人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/842 ,  G11C29/844 ,  G11C7/22 ,  G11C8/18

摘要： A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

摘要翻译： 在存储单元阵列附近提供将存储单元阵列中与所选存储单元对应的数据存储的数据寄存器。 从数据寄存器中选择数据的解码器响应于与确定操作周期的时钟信号同步地访问存储器单元的地址信号开始解码。 在时钟信号的运算周期的前半部分中，解码器响应于与前一操作周期中确定的地址信号对应的信号输出信号。 根据解码器的输出，选择数据寄存器。 在操作期间的后半部分，将与下一个操作期间的新的地址信号对应的信号传送到解码器。 通过这样做，使解码器中的输出控制信号与驱动地址信号的信号同步，使得能够选择合适的地址。

公开(公告)号：US5555523A

公开(公告)日：1996-09-10

申请号：US556148

申请日：1995-11-09

申请人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano ,  Kenji Numata

发明人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano ,  Kenji Numata

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4094

摘要： A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control circuit controls the equalizer and the precharger independently so that the precharger continues supplying the precharge potential to the first and second driving signal lines until essentially immediately before the driving signal supply circuit supplies the driving signal to the first and second driving signal lines.

摘要翻译： 半导体存储器件包括至少包括第一存储器单元和第二存储单元的多个存储器单元，连接到第一存储器单元的第一位线，连接到第二存储单元的第二位线，并与第一位配对 连接在第一和第二位线之间的均衡器，连接在第一和第二位线之间的放大器，连接到放大器并驱动放大器的第一驱动信号线，连接到放大器的第二驱动信号线， 第一驱动信号线，用于驱动放大器并连接到第一和第二驱动信号线并且包含用于将第一和第二驱动信号线的电位预设为预定预充电电位的预充电器的驱动器和用于 向第一和第二驱动信号线提供驱动信号，以及用于控制均衡器和驱动器的控制电路 r，其中控制电路独立地控制均衡器和预充电器，使得预充电器继续向第一和第二驱动信号线提供预充电电位，直到驱动信号提供电路将驱动信号提供给第一和第二驱动信号为止 线条。

公开(公告)号：US07712007B2

公开(公告)日：2010-05-04

申请号：US11531895

申请日：2006-09-14

申请人： Takeshi Nagai ,  Shinji Miyano

发明人： Takeshi Nagai ,  Shinji Miyano

IPC分类号： H03M13/00

CPC分类号： G06F11/106 ,  G11C2029/0411

摘要： When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuit by using the check bit. Before a normal operation mode is restored from the operation mode which performs only data holding, an error bit of the data is corrected by using the check bit. In an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation. Memory cells connected to a word line which is not accessed by the page mode operation are sequentially activated and refreshed.

摘要翻译： 当存储单元进入仅执行数据保持的操作模式时，控制电路如下控制存储单元和ECC电路。 读取多个数据以生成并存储用于错误检测和校正的校验位。 通过使用校验位，在由ECC电路执行的纠错操作的误差发生允许范围内的时间段内进行刷新。 在仅执行数据保持的操作模式恢复正常操作模式之前，通过使用校验位来校正数据的错误位。 在入口/出口期间，通过页面模式操作对所有存储器单元顺序执行读/写和ECC操作。 连接到不被页模式操作访问的字线的存储单元被依次激活和刷新。