公开(公告)号：US20060119415A1

公开(公告)日：2006-06-08

申请号：US11293378

申请日：2005-12-05

申请人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

发明人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

IPC分类号： H01H37/76

CPC分类号： H01L23/5258 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

摘要翻译： 一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为 并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

公开(公告)号：US07218560B2

公开(公告)日：2007-05-15

申请号：US11293378

申请日：2005-12-05

申请人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

发明人： Ryo Fukuda ,  Yohji Watanabe ,  Shuso Fujii

IPC分类号： G11C7/00

CPC分类号： H01L23/5258 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

摘要翻译： 一种半导体存储器件，包括：熔丝元件，包括第一端子和第二端子，该第一端子和第二端子基于其是否被激光束电熔接的数据，连接到第一端子的电阻元件，数据为 并且设置在电阻元件和节点之间的晶体管，其将数据设置到节点。

公开(公告)号：US5499211A

公开(公告)日：1996-03-12

申请号：US402442

申请日：1995-03-13

申请人： Toshiaki Kirihata ,  Shuso Fujii ,  Yohji Watanabe

发明人： Toshiaki Kirihata ,  Shuso Fujii ,  Yohji Watanabe

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C11/4094

摘要： A fault-tolerant DRAM design minimizes current flow in the even of a cross-fail. A bit-line precharge current limiter is provided for the bit-line precharge equalizer circuit. The bit-line precharge current limiter is both simple and effective, requiring very little silicon area to implement. The current limiter provides self current-limiting for defective bit-lines, without the necessity for a reference cell.

摘要翻译： 容错DRAM设计在即使交叉故障中也能最大限度地减少电流。 为位线预充电均衡电路提供位线预充电限流器。 位线预充电限流器既简单又有效，需要很少的硅面积来实现。 电流限制器为缺陷位线提供自限流，而不需要参考单元。

公开(公告)号：US20080079473A1

公开(公告)日：2008-04-03

申请号：US11864041

申请日：2007-09-28

申请人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

发明人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

IPC分类号： H03K3/356

CPC分类号： H03K3/356191 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

摘要翻译： 第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极 在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。 用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。 用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

公开(公告)号：US08027216B2

公开(公告)日：2011-09-27

申请号：US12550663

申请日：2009-08-31

申请人： Ryo Fukuda ,  Yohji Watanabe

发明人： Ryo Fukuda ,  Yohji Watanabe

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4016 ,  G11C2211/4067

摘要： A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

摘要翻译： 存储器可以包括：字线; 位线 存储器阵列块，包括存储器单元，每个存储器阵列块是数据读取操作或数据写入操作的单元; 行解码器，被配置为选择性地驱动所述字线; 配置成检测数据的感测放大器; 以及为每个存储器单元块提供的访问计数器，所述访问计数器对访问所述存储器阵列块的次数进行计数，以便读取数据或写入数据，以及当所述访问次数达到预定的次数时激活刷新请求信号 次数，其中在访问计数器的刷新请求信号的激活周期期间，行解码器周期性地并且顺序地激活对应于访问计数器的存储器阵列块的字线，并且读出放大器执行刷新操作 存储单元连接到激活的字线。

公开(公告)号：US07888769B2

公开(公告)日：2011-02-15

申请号：US11756196

申请日：2007-05-31

申请人： Masaki Kondo ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

发明人： Masaki Kondo ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

IPC分类号： H01L29/00

CPC分类号： H01L27/0251 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

摘要翻译： 根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

公开(公告)号：US07732840B2

公开(公告)日：2010-06-08

申请号：US11864041

申请日：2007-09-28

申请人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

发明人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

IPC分类号： H01L21/76

CPC分类号： H03K3/356191 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

摘要翻译： 第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极 在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。 用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。 用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

公开(公告)号：US20100074042A1

公开(公告)日：2010-03-25

申请号：US12550663

申请日：2009-08-31

申请人： Ryo FUKUDA ,  Yohji Watanabe

发明人： Ryo FUKUDA ,  Yohji Watanabe

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4016 ,  G11C2211/4067

摘要： A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

摘要翻译： 存储器可以包括：字线; 位线 存储器阵列块，包括存储器单元，每个存储器阵列块是数据读取操作或数据写入操作的单元; 行解码器，被配置为选择性地驱动所述字线; 配置成检测数据的感测放大器; 以及为每个存储器单元块提供的访问计数器，所述访问计数器对访问所述存储器阵列块的次数进行计数，以便读取数据或写入数据，以及当所述访问次数达到预定的次数时激活刷新请求信号 次数，其中在访问计数器的刷新请求信号的激活周期期间，行解码器周期性地并且顺序地激活对应于访问计数器的存储器阵列块的字线，并且读出放大器执行刷新操作 存储单元连接到激活的字线。

公开(公告)号：US20070278580A1

公开(公告)日：2007-12-06

申请号：US11756196

申请日：2007-05-31

申请人： Masaki KONDO ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

发明人： Masaki KONDO ,  Ryo Fukuda ,  Yohji Watanabe ,  Mitsutoshi Nakamura

IPC分类号： H01L23/62 ,  H02H3/20

CPC分类号： H01L27/0251 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

摘要翻译： 根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

公开(公告)号：US06603689B2

公开(公告)日：2003-08-05

申请号：US10045780

申请日：2002-01-11

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/787

摘要： A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.