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公开(公告)号：US20070262383A1
公开(公告)日：2007-11-15
申请号：US11767112
申请日：2007-06-22
IPC分类号： H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译： 半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。 第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。 此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。 第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。 因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。
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公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。
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公开(公告)号：US07091576B2
公开(公告)日：2006-08-15
申请号：US10460306
申请日：2003-06-13
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01L21/76838 , H01L23/5227 , H01L23/53228 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.
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公开(公告)号：US07256456B2
公开(公告)日：2007-08-14
申请号：US10739166
申请日：2003-12-19
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译： 半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。 第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。 此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。 第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。 因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。
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公开(公告)号：US20050139956A1
公开(公告)日：2005-06-30
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L21/8234 , H01L21/20 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。
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公开(公告)号：US06879234B2
公开(公告)日：2005-04-12
申请号：US10352048
申请日：2003-01-28
IPC分类号： H01F17/00 , H01F17/02 , H01L21/822 , H01L27/04 , H01L27/08 , H03B5/12 , H01F5/00 , H01F27/28
CPC分类号： H01L27/08 , H01F17/0006 , H01F2021/125 , H03B5/1215 , H03B5/1228 , H03B5/124
摘要： Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor. Since the areas defined by the loops forming these two inductors are equal to each other, the inductances of the inductors are also equal to each other. Between both the inductors, the lengths in the loop of the portions (the conductive layers 1a and 1b) formed on a lower interlayer insulating film are equal to each other, while the lengths in the loop of the portions (the conductive layers 2a and 2b) formed on an upper interlayer insulating film are also equal to each other. This allows external disturbances such as parasitic capacitance to affect both the inductors equally. Accordingly, a voltage controlled oscillator incorporating the invention can stably provide undistorted sinusoidal oscillation signals.
摘要翻译： 导电层1a和2a通过接触形成一个电感器，而导电层1b和2b通过其它触点相互连接形成另一个电感器。 由于由形成这两个电感器的环形成的区域彼此相等，所以电感器的电感也彼此相等。 在两个电感器之间，形成在下层间绝缘膜上的部分（导电层1a和1b）的环路中的长度彼此相等，而部分（导电层2a和2b）的环路中的长度 ）也相互相等。 这允许诸如寄生电容的外部干扰同样影响电感器。 因此，结合本发明的压控振荡器可以稳定地提供无失真的正弦振荡信号。
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公开(公告)号：US20060231923A1
公开(公告)日：2006-10-19
申请号：US11455678
申请日：2006-06-20
CPC分类号： H01L28/10 , H01L21/76838 , H01L23/5227 , H01L23/53228 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.
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公开(公告)号：US07339249B2
公开(公告)日：2008-03-04
申请号：US11066534
申请日：2005-02-28
申请人： Ryota Yamamoto , Yasutaka Nakashiba
发明人： Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L29/00
CPC分类号： H01L21/765 , H01L21/761 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p type silicon substrate is formed as a non-doped region with no impurity implanted. Then, a positive power supply potential is applied to the electrode. In this way, a depletion layer is formed directly under the electrode at the surface of the p type silicon substrate. Consequently, the substrate noise is shielded.
摘要翻译： 在p型硅衬底上的电路区域周围的区域中设置绝缘膜，并且设置框状电极以围绕绝缘膜上的电路区域。 在p型硅衬底的表面的正下方的区域形成为没有杂质注入的非掺杂区域。 然后，向电极施加正电源电位。 以这种方式，在p型硅衬底的表面下方的电极正下方形成耗尽层。 因此，衬底噪声被屏蔽。
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公开(公告)号：US20050189602A1
公开(公告)日：2005-09-01
申请号：US11066534
申请日：2005-02-28
申请人： Ryota Yamamoto , Yasutaka Nakashiba
发明人： Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L21/76 , H01L21/761 , H01L21/765 , H01L21/822 , H01L23/58 , H01L27/04 , H01L29/00 , H01L29/06 , H01L29/51 , H01L29/74 , H01L31/111
CPC分类号： H01L21/765 , H01L21/761 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p type silicon substrate is formed as a non-doped region with no impurity implanted. Then, a positive power supply potential is applied to the electrode. In this way, a depletion layer is formed directly under the electrode at the surface of the p type silicon substrate. Consequently, the substrate noise is shielded.
摘要翻译： 在p型硅衬底上的电路区域周围的区域中设置绝缘膜，并且设置框状电极以围绕绝缘膜上的电路区域。 在p型硅衬底的表面的正下方的区域形成为没有杂质注入的非掺杂区域。 然后，向电极施加正电源电位。 以这种方式，在p型硅衬底的表面下方的电极正下方形成耗尽层。 因此，衬底噪声被屏蔽。
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10.发明授权Semiconductor device including metal-insulator-metal capacitor arrangement 失效半导体器件包括金属 - 绝缘体 - 金属电容器布置公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。
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