公开(公告)号：US06768741B1

公开(公告)日：2004-07-27

申请号：US09559724

申请日：2000-04-28

申请人： Ryouichi Bandai ,  Masahiko Motoyama

发明人： Ryouichi Bandai ,  Masahiko Motoyama

IPC分类号： H04L1228

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/255 ,  H04L2012/5629 ,  H04L2012/5636 ,  H04L2012/5682

摘要： There is provided a compact ATM switch. Each of the bit values of at least one of counters for counting the number of ATM cells in a cell buffer is set to be “H” when the at least one of counters is preset.

摘要翻译： 提供了一个紧凑的ATM交换机。 当预定了至少一个计数器时，用于对单元缓冲器中的ATM信元的数量进行计数的计数器中的至少一个的位值的每个值被设置为“H”。

公开(公告)号：US08145963B2

公开(公告)日：2012-03-27

申请号：US12533639

申请日：2009-07-31

申请人： Keiko Fukuda ,  Yoshinori Watanabe ,  Ryouichi Bandai

发明人： Keiko Fukuda ,  Yoshinori Watanabe ,  Ryouichi Bandai

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/318594

摘要： A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

摘要翻译： 半导体集成电路器件包括：第一时钟域，具有多个第一触发器，其被配置为以高速时钟进行操作; 具有由第三触发器和多个第四触发器组成的多个第二触发器的第二时钟域，其被配置为以低速时钟进行操作; 以及测试时钟提供部分，被配置为在第二时钟域的延迟故障测试时，向输入来自第一时钟域的数据的第三触发器提供基于高速时钟的测试时钟， 并且不向多个第四触发器提供测试时钟。

公开(公告)号：US20100095170A1

公开(公告)日：2010-04-15

申请号：US12533639

申请日：2009-07-31

申请人： Keiko FUKUDA ,  Yoshinori Watanabe ,  Ryouichi Bandai

发明人： Keiko FUKUDA ,  Yoshinori Watanabe ,  Ryouichi Bandai

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/318594

摘要： A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

摘要翻译： 半导体集成电路器件包括：第一时钟域，具有多个第一触发器，其被配置为以高速时钟进行操作; 具有由第三触发器和多个第四触发器组成的多个第二触发器的第二时钟域，其被配置为以低速时钟进行操作; 以及测试时钟提供部分，被配置为在第二时钟域的延迟故障测试时，向输入来自第一时钟域的数据的第三触发器提供基于高速时钟的测试时钟， 并且不向多个第四触发器提供测试时钟。

公开(公告)号：US06788698B1

公开(公告)日：2004-09-07

申请号：US09533592

申请日：2000-03-23

申请人： Ryouichi Bandai ,  Kenji Sakaue ,  Yasuo Unekawa ,  Yuichi Miyazawa

发明人： Ryouichi Bandai ,  Kenji Sakaue ,  Yasuo Unekawa ,  Yuichi Miyazawa

IPC分类号： H04L1228

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/30 ,  H04L2012/5651 ,  H04L2012/5682

摘要： It is an object of the present invention to provide a data switching method capable of impartially selecting a plurality of input ports by a simple circuit configuration. The data switching method according to the present invention includes an up-counter, a down-counter, a counter selecting circuit for selecting either of a counted value by the up-counter or a counted value by the down-counter, a port selecting circuit for selecting one of a plurality of input ports based on an output from the counter selecting circuit, and a buffer for accumulating a packet supplied from the input port selected by the port selecting circuit. The port selecting circuit alternately selects the up-counter and the down-counter to switch the ascending order and the descending order of the import priority of the input ports at every time the packet is imported, thereby impartially selecting each of the input ports.

摘要翻译： 本发明的目的是提供一种能够通过简单的电路配置公正地选择多个输入端口的数据切换方法。 根据本发明的数据交换方法包括：递增计数器，递减计数器，用于通过递增计数器选择计数值中的任何一个的计数器选择电路或通过递减计数器选择计数值的计数器选择电路;端口选择电路 用于基于来自计数器选择电路的输出来选择多个输入端口中的一个，以及用于累加由端口选择电路选择的输入端口提供的分组的缓冲器。 端口选择电路交替地选择递增计数器和递减计数器，以在每次输入数据包时切换输入端口的导入优先级的升序和降序，从而公正地选择每个输入端口。

公开(公告)号：US6081145A

公开(公告)日：2000-06-27

申请号：US96104

申请日：1998-06-11

申请人： Ryouichi Bandai ,  Kenji Sakaue ,  Keiko Fukuda

发明人： Ryouichi Bandai ,  Kenji Sakaue ,  Keiko Fukuda

IPC分类号： G06F1/10 ,  G11C11/4076 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K3/02 ,  H03K5/13 ,  H03L7/06 ,  H03K3/00

CPC分类号： G06F1/10

摘要： A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.

摘要翻译： 半导体集成电路器件具有多个功能块。 多个功能块中的每一个包括用于输出时钟信号的DLL电路，用于在其一端接收时钟信号的至少一个布线部分和用于经由布线从DLL电路接收时钟信号的至少一个负载电路 一部分。 DLL电路接收参考时钟信号和布线部分，并输出时钟信号，使得参考时钟信号和第二时钟信号之间的相位差为预定值。 因此，即使由于处理而存在变化，时钟偏移也减小。