公开(公告)号：US06707735B2

公开(公告)日：2004-03-16

申请号：US10120445

申请日：2002-04-12

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

摘要翻译： 当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。 通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。 提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

公开(公告)号：USRE41245E1

公开(公告)日：2010-04-20

申请号：US11148452

申请日：2005-06-09

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2207/2227

摘要： Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.

摘要翻译： 通过命令模式检测电路检测指定的最终地址的连续数据读取访问以设置命令模式输入状态。 在命令模式输入中，根据预定的外部信号使指定内部状态的命令成为可接受的命令。 因此，提供了进入指令模式，保持引脚和信号定时与常规状态存储器的兼容性的半导体存储器件。

公开(公告)号：US06795943B2

公开(公告)日：2004-09-21

申请号：US09973894

申请日：2001-10-11

申请人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

发明人： Hirotoshi Sato ,  Masaki Tsukude ,  Ryu Makabe

IPC分类号： G01R3128

CPC分类号： G11C29/14

摘要： A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

摘要翻译： 半导体存储器包括：第一解码器，根据第一至第四数据信号选择测试模式B的模式1-n中的任何一个;以及第二解码器，根据第五至第八数据信号选择测试模式B的模式1-n中的任何一个 。 当在测试模式A中未设置预定模式m + 1时，设置由第一和第二解码器选择的模式。 当设定了预定模式m + 1时，设置由第一解码器选择的模式。 因此，通过将四个数据输入/输出端子连接到测试器，可以在制造商侧设置测试模式B.

公开(公告)号：US06577553B2

公开(公告)日：2003-06-10

申请号：US10123167

申请日：2002-04-17

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2207/2227

摘要： Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

公开(公告)号：US06556485B2

公开(公告)日：2003-04-29

申请号：US09972242

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

公开(公告)号：US06891770B2

公开(公告)日：2005-05-10

申请号：US10920421

申请日：2004-08-18

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C11/406 ,  G11C11/408

摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

摘要翻译： 响应于地址转换检测信号的前沿和后沿来控制用于控制存储器单元选择操作的内部正常行激活信号的激活/去激活。 当内部正常行激活信号被激活时，地址转换检测信号的产生被掩码电路掩蔽。 可以防止激活操作和正常行激活信号的失活操作之间的冲突，并且可以稳定地执行内部操作。 提供了一种具有与静态随机存取存储器兼容并且能够稳定地执行内部操作的接口的无刷新的动态半导体存储器件。

公开(公告)号：US06882586B2

公开(公告)日：2005-04-19

申请号：US10267670

申请日：2002-10-10

申请人： Hirotoshi Sato ,  Masaki Tsukude

发明人： Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C29/14 ,  G11C7/00

CPC分类号： G11C29/12015 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C29/14

摘要： A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.

摘要翻译： 半导体存储器件设置有存储单元阵列，其包括以矩阵形状布置并需要刷新操作的存储单元。 在半导体存储装置中，控制电路根据与外部信号无关的内部信号来控制刷新动作的定时，并将存储单元阵列控制在与将数据写入的通常动作模式不同的非正常动作模式 存储单元阵列并从存储单元阵列中读出数据。 控制电路响应于基于预定的第一命令信号进入非正常操作模式的顺序而开始非正常操作模式，响应于非正常设置的顺序设置非正常操作模式 基于预定的第二命令信号进行操作模式，然后执行设定的相应的非正常操作模式的操作。

公开(公告)号：US07145832B2

公开(公告)日：2006-12-05

申请号：US11429291

申请日：2006-05-08

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C8/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

公开(公告)号：US07061828B2

公开(公告)日：2006-06-13

申请号：US11215994

申请日：2005-09-01

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C8/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

公开(公告)号：US06859415B2

公开(公告)日：2005-02-22

申请号：US10352218

申请日：2003-01-28

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.