公开(公告)号：US20160116939A1

公开(公告)日：2016-04-28

申请号：US14989575

申请日：2016-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BO-GEUN KIM ,  KYE-HYUN KYUNG ,  JAE-YONG JEONG ,  SEUNG-HUN CHOI ,  SEOK-CHEON KWON ,  CHUL-HO LEE

IPC: G06F1/12 ,  G06F3/06

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract translation: 一种存储器系统，包括产生处理器时钟的控制器，以及多个存储器件，每个存储器件包括与所述处理器时钟同步地产生内部时钟的内部时钟发生器，以及与所述处理器时钟同步地执行峰值电流产生操作的存储器 内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

公开(公告)号：US20160125939A1

公开(公告)日：2016-05-05

申请号：US14806780

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON ,  BO-GEUN KIM

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/77

Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

Abstract translation: 提供了包括多个存储单元的电阻式存储器件以及操作该电阻式存储器件的方法。 电阻式存储器件包括连接到存储单元连接到的第一信号线的感测电路，感测电路基于第一参考电流感测存储在存储器单元中的数据; 以及参考时间发生器，用于产生基于所述第一参考电流确定所述感测的结果的时间点的参考时间信号。

公开(公告)号：US20160019951A1

公开(公告)日：2016-01-21

申请号：US14665127

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-KOOK PARK ,  DAE-SEOK BYEON ,  YEONG-TAEK LEE ,  BO-GEUN KIM ,  YONG-KYU LEE ,  HYO-JIN KWON

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/025 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2213/71

Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括多个垂直层叠的层，其中一层被指定为无干扰层，另一层指定为禁止访问层，其中无干扰层和禁止访问层共享与 禁止至少一条信号线和针对存储器单元访问禁止层的访问操作。