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    Memory device having sub wordline driver
    1.
    发明授权
    Memory device having sub wordline driver 有权

    公开(公告)号：US12106795B2

    公开(公告)日：2024-10-01

    申请号：US17724006

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeongsik Ryu ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408

    CPC classification number: G11C11/4085

    Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

    Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices
    2.
    发明授权
    Time interleaved sampling of sense amplifier circuits, memory devices and methods of operating memory devices 有权

    公开(公告)号：US11024365B1

    公开(公告)日：2021-06-01

    申请号：US16782365

    申请日：2020-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Younghun Seo ,  Bokyeon Won ,  Dongil Lee

    IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094

    Abstract: Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.

    Integrated circuit devices
    4.
    发明授权
    Integrated circuit devices 有权

    公开(公告)号：US11437089B2

    公开(公告)日：2022-09-06

    申请号：US17245334

    申请日：2021-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taesung Kang ,  Youngkyu Lee ,  Kyoungmin Kim ,  Ilgweon Kim ,  Bokyeon Won ,  Seokjae Lee ,  Sungho Jang ,  Joon Han

    IPC: G11C11/4091 ,  H01L27/108

    Abstract: An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT
    7.
    发明申请
    MEMORY DEVICE INCLUDING SUB WORD LINE DRIVING CIRCUIT 有权

    公开(公告)号：US20220406361A1

    公开(公告)日：2022-12-22

    申请号：US17828200

    申请日：2022-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inseok Baek ,  Bokyeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Seokjae Lee

    IPC: G11C11/408

    Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

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