公开(公告)号：US20150339059A1

公开(公告)日：2015-11-26

申请号：US14436344

申请日：2014-10-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byoungik KANG ,  Jinyoung PARK ,  Heesub SHIN ,  Seungwook LEE

IPC分类号： G06F3/06

CPC分类号： G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023 ,  G06F2212/401

摘要： Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

摘要翻译： 公开了一种电子设备的记忆压缩方法及其装置。 用于压缩电子设备中的存储器的方法可以包括：检测执行第一应用的请求; 确定所述存储器压缩是否需要用于执行所述第一应用; 当需要存储器压缩时，在电子设备的背景中对与应用程序相对应的存储器进行压缩; 并执行第一应用。

公开(公告)号：US20180300063A1

公开(公告)日：2018-10-18

申请号：US16018790

申请日：2018-06-26

申请人： Samsung Electronics Co., Ltd.

发明人： Byoungik KANG ,  Jinyoung PARK ,  Heesub SHIN ,  Seungwook LEE

IPC分类号： G06F3/06 ,  G06F12/02

摘要： Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

公开(公告)号：US20180357417A1

公开(公告)日：2018-12-13

申请号：US15775519

申请日：2016-10-31

申请人： Samsung Electronics Co., Ltd.

发明人： Byoungik KANG ,  Minsoo KIM ,  Wonjin KIM ,  Philkoo YEO ,  Sangchul JUNG ,  Taedong JUNG

IPC分类号： G06F21/55

CPC分类号： G06F21/554 ,  G06F21/566 ,  G06F21/70 ,  G06F2221/034 ,  H04L29/06

摘要： A method for operating an apparatus according to various embodiments may comprise the operations of: detecting whether a first signal transmitted from a control device to a storage device includes a designated address; and transmitting a second signal to the control device if the first signal includes the designated address, wherein the first signal may be a signal for transmitting, by the control device, a request for data to the storage device, and the second signal may be a signal for detecting whether uncommon data is included in a signal generated from the first signal.

公开(公告)号：US20170070516A1

公开(公告)日：2017-03-09

申请号：US15255469

申请日：2016-09-02

申请人： Samsung Electronics Co., Ltd.

发明人： Byoungik KANG ,  Minsoo KIM ,  Wonjin KIM ,  Philkoo YEO ,  Sangchul JUNG ,  Taedong JUNG

IPC分类号： H04L29/06 ,  G06F12/0813

CPC分类号： H04L63/1416 ,  G06F12/0813 ,  G06F2212/154 ,  G06F2212/60 ,  G06F2212/62 ,  H04L47/2441 ,  H04W84/105 ,  H04W84/12

摘要： An apparatus and a method for processing data are provided. The method for processing data by a terminal. The method includes identifying a plurality of inspection types for a packet; determining at least one inspection type from the plurality of inspection types for the packet based on a predetermined criterion; and processing the determined at least one inspection type for the packet.

摘要翻译： 提供了一种用于处理数据的装置和方法。 终端处理数据的方法。 该方法包括识别分组的多个检查类型; 基于预定标准从所述分组的所述多个检查类型中确定至少一个检查类型; 以及处理所确定的所述分组的至少一个检查类型。

公开(公告)号：US20150261683A1

公开(公告)日：2015-09-17

申请号：US14643046

申请日：2015-03-10

申请人： Samsung Electronics Co., Ltd.

发明人： Eunseok HONG ,  Byoungik KANG ,  Gilyoon KIM ,  Jinyoung PARK ,  Seungjin YANG ,  Jinyong JANG ,  Chunmok CHUNG ,  Jin CHOI

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0895

摘要： Disclosed are a method and apparatus for controlling a cache memory in an electronic device. The apparatus includes a cache memory having cache lines, each of which includes tag information and at least two sub-lines. Each of the at least two sub-lines including a valid bit and a dirty bit. A control unit may analyze a valid bit of a sub-line corresponding to an address tag of data when a request for writing the data is sensed, determine based on activation or deactivation of the valid bit whether a cache hit or a cache miss occurs, and perform a control operation for allocating a sub-line according to a size of the requested data and write the data when the cache hit occurs.

摘要翻译： 公开了一种用于控制电子设备中的高速缓冲存储器的方法和装置。 该装置包括具有高速缓存行的高速缓冲存储器，每个高速缓存行包括标签信息和至少两个子行。 所述至少两条子线中的每一条包括有效位和脏位。 当感测到写入数据的请求时，控制单元可以分析对应于数据的地址标签的子线的有效位，基于是否发生高速缓存命中或高速缓存未命中来确定有效位的激活或去激活， 并且执行用于根据所请求数据的大小分配子行的控制操作，并且在发生高速缓存命中时写入数据。