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公开(公告)号：US10009166B2
公开(公告)日：2018-06-26
申请号：US15602239
申请日：2017-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwang-Chun Choi , Jong-Shin Shin , Sung-Jun Kim , Hye-Yeon Yang , Byung-Hyun Lim , Woo-Chul Jung
CPC classification number: H04L7/0041 , H03K3/0315 , H03K3/356 , H03K5/26 , H03L7/0807 , H03L7/085 , H03L7/089 , H03L7/091 , H03L7/0991 , H03L7/0995 , H04L7/0037 , H04L7/0087 , H04L7/033
Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.
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公开(公告)号：US20180152283A1
公开(公告)日：2018-05-31
申请号：US15602239
申请日：2017-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwang-Chun Choi , Jong-Shin Shin , Sung-Jun Kim , Hye-Yeon Yang , Byung-Hyun Lim , Woo-Chul Jung
CPC classification number: H04L7/0041 , H03K3/0315 , H03K3/356 , H03K5/26 , H03L7/0807 , H03L7/085 , H03L7/0991 , H04L7/0037 , H04L7/0087
Abstract: A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.
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