公开(公告)号：US10026747B2

公开(公告)日：2018-07-17

申请号：US15239121

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Jin Hwang ,  Pan-Suk Kwak ,  Seok-Jun Ham

IPC: G11C29/24 ,  G11C29/02 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/02 ,  H01L49/02

Abstract: A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

公开(公告)号：US09589643B2

公开(公告)日：2017-03-07

申请号：US15226941

申请日：2016-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Jin Hwang ,  Pansuk Kwak ,  Younghwan Ryu

IPC: G11C16/04 ,  G11C16/08 ,  H01L27/115

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括在与衬底正交的方向上堆叠的单元串，并且包括分隔单元串的第一子串组和第二子串组以及经由单元串连接到单元串的存储单元的地址解码器 多个字线并且被配置为向存储器单元提供工作电压，其中地址解码器设置在第一子串组和第二子串组之间。

公开(公告)号：US09424928B2

公开(公告)日：2016-08-23

申请号：US14817281

申请日：2015-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Jin Hwang ,  Pansuk Kwak ,  Younghwan Ryu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括在与衬底正交的方向上堆叠的单元串，并且包括分隔单元串的第一子串组和第二子串组以及经由单元串连接到单元串的存储单元的地址解码器 多个字线并且被配置为向存储器单元提供工作电压，其中地址解码器设置在第一子串组和第二子串组之间。