公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US11830541B2

公开(公告)日：2023-11-28

申请号：US17569679

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/14

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US10147481B2

公开(公告)日：2018-12-04

申请号：US15292834

申请日：2016-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daero Kim

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16

Abstract: A clean data strobe signal generating circuit in a read interface device includes receivers configured to output first and second single ended data strobe signals. In the circuit, a gate signal generating unit is configured to generate a data strobe gate signal synchronized with the first single ended data strobe signal using the first and second single ended data strobe signals and a memory gate signal of which the pulse width varies in accordance with a burst length after termination of a read latency. The gating unit is configured to generate a clean data strobe signal using the first single ended data strobe signal and the data strobe gate signal.