公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US11830541B2

公开(公告)日：2023-11-28

申请号：US17569679

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/14

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US20240046982A1

公开(公告)日：2024-02-08

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero KIM ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US12218639B2

公开(公告)日：2025-02-04

申请号：US17588617

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyeon Park ,  Kihwan Seong

IPC: H03F1/56 ,  H03F3/45

Abstract: An interface circuit includes a first amplifier circuit comprising a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, a first output node configured to output a first output signal, a second output node configured to output a second output signal, and a variable impedance circuit comprising a first impedance circuit connected to the first output node, and a second impedance circuit connected to the second output node. A code generator circuit is configured to generate a first control code and a second control code. The first impedance circuit is configured to adjust an impedance thereof based on the first control code, and the second impedance circuit is configured to adjust an impedance thereof based on the second control code.

公开(公告)号：US20220286095A1

公开(公告)日：2022-09-08

申请号：US17588617

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyeon Park ,  Kihwan Seong

IPC: H03F1/56 ,  H03F3/45

Abstract: An interface circuit includes a first amplifier circuit comprising a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, a first output node configured to output a first output signal, a second output node configured to output a second output signal, and a variable impedance circuit comprising a first impedance circuit connected to the first output node, and a second impedance circuit connected to the second output node. A code generator circuit is configured to generate a first control code and a second control code. The first impedance circuit is configured to adjust an impedance thereof based on the first control code, and the second impedance circuit is configured to adjust an impedance thereof based on the second control code.