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公开(公告)号：US11830541B2
公开(公告)日：2023-11-28
申请号：US17569679
申请日：2022-01-06
发明人： Daero Kim , Kyunghoi Koo , Sujeong Kim , Juyoung Kim , Sanghune Park , Jiyeon Park , Jihun Oh , Kyoungwon Lee
IPC分类号： G11C11/4076 , G11C11/4096 , G06F13/16 , G11C7/10 , G11C11/4093 , G11C7/14
CPC分类号： G11C11/4096 , G11C11/4076 , G06F13/1689 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/14 , G11C11/4093
摘要： A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
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公开(公告)号：US12081230B2
公开(公告)日：2024-09-03
申请号：US17871538
申请日：2022-07-22
发明人： Kyoungwon Lee , Jintae Kim , Sungwon Roh
CPC分类号： H03M1/365
摘要： An analog-to-digital converter (ADC) for converting an analog signal into a digital signal includes an amplifier circuit configured to receive the analog signal, and to generate a plurality of amplifier signals by amplifying the analog signal; a comparison circuit configured to compare a plurality of voltage levels corresponding to the plurality of amplifier signals with a positive reference voltage level and a negative reference voltage level, and to output conversion target signals based on a result of the comparison; and a converter circuit configured to convert the conversion target signals into a plurality of digital signals.
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公开(公告)号：US20240046982A1
公开(公告)日：2024-02-08
申请号：US18490042
申请日：2023-10-19
发明人： Daero KIM , Kyunghoi Koo , Sujeong Kim , Juyoung Kim , Sanghune Park , Jiyeon Park , Jihun Oh , Kyoungwon Lee
IPC分类号： G11C11/4096 , G11C11/4076
CPC分类号： G11C11/4096 , G11C11/4076 , G06F13/1689
摘要： A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
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公开(公告)号：US12119049B2
公开(公告)日：2024-10-15
申请号：US18490042
申请日：2023-10-19
发明人： Daero Kim , Kyunghoi Koo , Sujeong Kim , Juyoung Kim , Sanghune Park , Jiyeon Park , Jihun Oh , Kyoungwon Lee
IPC分类号： G11C11/4076 , G11C11/4096 , G06F13/16 , G11C7/10 , G11C7/14 , G11C11/4093
CPC分类号： G11C11/4096 , G11C11/4076 , G06F13/1689 , G11C7/1066 , G11C7/1084 , G11C7/1093 , G11C7/14 , G11C11/4093
摘要： A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.
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