公开(公告)号：US09991281B2

公开(公告)日：2018-06-05

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US08962444B2

公开(公告)日：2015-02-24

申请号：US14053913

申请日：2013-10-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  Hunhyeong Lim

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

公开(公告)号：US11339473B2

公开(公告)日：2022-05-24

申请号：US16522372

申请日：2019-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yub Ie ,  Guk-Hyon Yon ,  Jung-Geun Jee

IPC: C23C16/48 ,  C23C16/455 ,  H01L21/02 ,  C23C16/24 ,  C23C16/52

Abstract: An ALD apparatus includes a first process chamber configured to supply a first source gas and induce adsorption of a first material film. A second process chamber is configured to supply a second source gas and induce adsorption of a second material film. A third process chamber is configured to supply a third source gas and induce absorption of a third material film. A surface treatment chamber is configured to perform a surface treatment process on each of the first to third material films and remove a reaction by-product. A heat treatment chamber is configured to perform a heat treatment process on the substrate on which the first to third material films are adsorbed in a predetermined order and transform the first to third material films into a single compound thin film.

公开(公告)号：US09754959B2

公开(公告)日：2017-09-05

申请号：US14963987

申请日：2015-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US20170358596A1

公开(公告)日：2017-12-14

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-MI YUN ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.