公开(公告)号：US20170358596A1

公开(公告)日：2017-12-14

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-MI YUN ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US09991281B2

公开(公告)日：2018-06-05

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US09754959B2

公开(公告)日：2017-09-05

申请号：US14963987

申请日：2015-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US11171287B2

公开(公告)日：2021-11-09

申请号：US16365874

申请日：2019-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Uk Kim ,  Young-Min Ko ,  Byong-Ju Kim ,  Kwang-Min Park ,  Jeong-Hee Park ,  Dong-Sung Choi

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device may include a memory unit including a first electrode disposed on a substrate, a variable resistance pattern disposed on the first electrode and a second electrode disposed on the variable resistance pattern, a selection pattern disposed on the memory unit, and a capping structure covering a sidewall of the selection pattern. The capping structure may include a first capping pattern and a second capping pattern sequentially stacked on at least one sidewall of the selection pattern. The first capping pattern may be silicon pattern, and the second capping pattern may include a nitride.