公开(公告)号：US09754959B2

公开(公告)日：2017-09-05

申请号：US14963987

申请日：2015-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US09536896B2

公开(公告)日：2017-01-03

申请号：US14674583

申请日：2015-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon Lee ,  Jin-Gyun Kim ,  Hyun Namkoong ,  Ki-Hyun Hwang ,  Hun-Hyeong Lim ,  Dong-Kyum Kim

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract translation: 具有垂直结构的非易失性存储器件包括半导体层，在半导体层上沿垂直方向延伸的侧壁绝缘层，并且具有一个或多个突出区域，在半导体层上沿垂直方向布置的第一控制栅电极 并且分别接触在半导体层上形成有一个或多个突起区域的侧壁绝缘层的一部分和在垂直方向上排列的第二控制栅电极，并分别接触一个或多个突出区域中的一个。

公开(公告)号：US20170358596A1

公开(公告)日：2017-12-14

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-MI YUN ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US09793291B2

公开(公告)日：2017-10-17

申请号：US15142365

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jin Shin ,  Hong-Suk Kim ,  Jung-Hwan Kim ,  Sang-Hoon Lee ,  Hun-Hyeong Lim ,  Yong-Seok Cho ,  Young-Dae Kim ,  Han-Vit Yang

IPC: H01L21/336 ,  H01L27/11582 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11568 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

公开(公告)号：US09991281B2

公开(公告)日：2018-06-05

申请号：US15671370

申请日：2017-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Mi Yun ,  Young-Jin Noh ,  Kwang-Min Park ,  Jae-Young Ahn ,  Guk-Hyon Yon ,  Dong-Chul Yoo ,  Joong-Yun Ra ,  Young-Seon Son ,  Jeon-Il Lee ,  Hun-Hyeong Lim

IPC: H01L29/788 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7883

Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.

公开(公告)号：US09276133B2

公开(公告)日：2016-03-01

申请号：US14184262

申请日：2014-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Jun-Kyu Yang ,  Hun-Hyeong Lim ,  Jae-ho Choi ,  Ki-Hyun Hwang

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

Abstract translation: 公开了制造垂直存储器件的方法。 在该方法中，多个绝缘层和多个第一牺牲层交替堆叠在基板上。 通过多个绝缘层和第一牺牲层形成多个孔。 进行等离子体处理工艺以氧化由孔暴露的第一牺牲层。 多个第二牺牲层图案从孔的侧壁突出。 在覆盖第二牺牲层图案的孔的侧壁上形成阻挡层图案，电荷存储层图案和隧道绝缘层图案。 形成多个通道以填充孔。 去除第一牺牲层和第二牺牲层图案以形成暴露阻挡层图案的侧壁的多个间隙。 形成多个栅电极以填充间隙。