公开(公告)号：US20180308859A1

公开(公告)日：2018-10-25

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/7926

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US20190081054A1

公开(公告)日：2019-03-14

申请号：US15981928

申请日：2018-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGGIL KIM ,  SANGSOO LEE ,  SEULYE KIM ,  HONGSUK KIM ,  JINTAE NOH ,  JI-HOON CHOI ,  JAEYOUNG AHN ,  SANGHOON LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

公开(公告)号：US20190333937A1

公开(公告)日：2019-10-31

申请号：US16509169

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HOON CHOI ,  SUNGGIL KIM ,  SEULYE KIM ,  HONGSUK KIM ,  PHIL OUK NAM ,  JAEYOUNG AHN

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.