公开(公告)号：US11874784B2

公开(公告)日：2024-01-16

申请号：US18089148

申请日：2022-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20240111695A1

公开(公告)日：2024-04-04

申请号：US18538263

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20240296876A1

公开(公告)日：2024-09-05

申请号：US18465416

申请日：2023-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： YongHyun An ,  Hae Young Chung ,  Soyeong Shin

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1084 ,  G11C7/1012 ,  G11C7/14 ,  G11C2207/2254

Abstract: A memory device includes a memory cell array and an input/output circuit. The input/output circuit is configured to: (i) generate second data in response to sampling first data by comparing the first data against a reference voltage, (ii) generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code, (iii) change a gain of an input buffer corresponding to the mode register code after receiving the mode register code, and (iv) calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code. Control logic may also be used to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.

公开(公告)号：US11567886B2

公开(公告)日：2023-01-31

申请号：US17008121

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su Jeong ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20240290378A1

公开(公告)日：2024-08-29

申请号：US18461550

申请日：2023-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae Young Chung

IPC: G11C11/4096 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C2207/2245

Abstract: Disclosed is a memory device, which comprises a memory cell array that includes a plurality of memory cells; an input/output circuit configured to transmit data received from an outside (e.g., an external source) through a data pad to the memory cell array or transmit data read from the memory cell array to the external source; and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input/output circuit. The impedance calibration circuit is further configured to divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.