公开(公告)号：US12080691B2

公开(公告)日：2024-09-03

申请号：US17585122

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Park ,  Heonwoo Kim ,  Sangcheon Park ,  Wonil Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/37001

Abstract: A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

公开(公告)号：US11881456B2

公开(公告)日：2024-01-23

申请号：US17535887

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heonwoo Kim

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L23/5385 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor package includes; an interposer mounted on a package substrate, a first semiconductor device and a second semiconductor device mounted on the interposer, a molding member including an outer side wall portion covering an outer side surface of the first semiconductor device, and a lower portion covering at least a portion of an upper surface of the interposer, and a capping structure including an outer side wall portion covering the outer side wall portion of the molding member.

公开(公告)号：US11848307B2

公开(公告)日：2023-12-19

申请号：US17478247

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Park ,  Ungcheon Kim ,  Heonwoo Kim ,  Yunseok Choi

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/562

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.