公开(公告)号：US20240321744A1

公开(公告)日：2024-09-26

申请号：US18612137

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jiyoung Park ,  Hosin Song ,  Sera Lee

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/532 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/1436

Abstract: The present disclosure relates to semiconductor packages. An example semiconductor package includes a substrate including an active surface and an inactive surface, a plurality of wiring structures arranged on the active surface of the substrate, an inter-wiring insulating layer arranged on the active surface of the substrate and configured to cover the plurality of wiring structures, a modified layer including both side surfaces thereof covered by the inter-wiring insulating layer and including a carbonized material, and a passivation layer arranged on the inter-wiring insulating layer and the modified layer.

公开(公告)号：US20230386949A1

公开(公告)日：2023-11-30

申请号：US18067060

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Park ,  Yeongkwon Ko ,  Hosin Song

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L24/24 ,  H01L25/105 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49822 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L24/16 ,  H01L2224/16227 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/24996 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2224/245

Abstract: A semiconductor package includes a semiconductor chip on a redistribution substrate and including a body, a chip pad on the body, and a pillar on the chip pad, a connection substrate including base layers and a lower pad on a bottom surface of a lowermost one of the base layers, a first passivation layer between the semiconductor chip and the redistribution substrate, and a dielectric layer between the redistribution substrate and the connection substrate. The first passivation layer and the dielectric layer include different materials from each other. A bottom surface of the pillar, a bottom surface of the first passivation layer, a bottom surface of a molding layer, a bottom surface of the lower pad, and a bottom surface of the dielectric layer are coplanar with each other.