公开(公告)号：US20240145444A1

公开(公告)日：2024-05-02

申请号：US18219396

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiju Lee ,  Jinsu Kim ,  Hyunsuk Yang ,  Byoungwook Jang

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package is provided and includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, wherein the first redistribution pattern includes a first redistribution via extending in a vertical direction within the first redistribution insulating layer; a second redistribution structure on the first redistribution structure and including a second redistribution pattern and a second redistribution insulating layer, wherein the second redistribution pattern includes a lower redistribution pad at a lower surface of the second redistribution insulating layer; a first semiconductor chip on the second redistribution structure; and a second semiconductor chip on the first semiconductor chip. An upper surface of the first redistribution insulating layer is in contact with the lower surface of the second redistribution insulating layer, and the the first redistribution via of the first redistribution structure is in contact with the lower redistribution pad of the second redistribution structure.

公开(公告)号：US11824033B2

公开(公告)日：2023-11-21

申请号：US18149342

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/13005 ,  H01L2224/13024 ,  H01L2224/2105 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73217 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US11552038B2

公开(公告)日：2023-01-10

申请号：US17342902

申请日：2021-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US11508598B2

公开(公告)日：2022-11-22

申请号：US17007883

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungwan Kim ,  Hyunsuk Yang

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/56 ,  H01L21/67 ,  H01L21/60

Abstract: A frame jig for manufacturing a semiconductor package includes a frame body of a rectangular shape attached to a package structure of a panel shape, wherein the frame body comprises polyphenylene sulfide.

公开(公告)号：US20230133567A1

公开(公告)日：2023-05-04

申请号：US18149342

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung JUNG ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/00

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.