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公开(公告)号:US12132501B2
公开(公告)日:2024-10-29
申请号:US17895227
申请日:2022-08-25
发明人: Wonjae Shin , Sung-Joon Kim , Heedong Kim , Minsu Bae , Ilwoong Seo , Mijin Lee , Seung Ju Lee , Hyan Suk Lee , Insu Choi , Kideok Han
IPC分类号: H03M13/19 , G06F11/10 , G11C5/04 , G11C8/08 , G11C11/408 , G11C11/4096 , G11C29/52 , H03M13/00
CPC分类号: H03M13/19 , G06F11/10 , G06F11/1012 , G06F11/1044 , G06F11/1048 , G11C8/08 , G11C11/4085 , G11C11/4096 , G11C29/52 , H03M13/611 , G11C5/04
摘要: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.