公开(公告)号：US20140253188A1

公开(公告)日：2014-09-11

申请号：US14193595

申请日：2014-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hun-Dae CHOI ,  In-Dal SONG

IPC: H03K21/00

CPC classification number: H03K23/42 ,  H03K23/667

Abstract: A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

Abstract translation: 时钟生成装置包括触发器，时钟分割单元和时钟比较器。 触发器产生与内部时钟信号同步的芯片选择信号。 时钟分割单元基于第一分频时钟信号产生第二分频时钟信号。 时钟比较器基于芯片选择信号选择第二分频时钟信号中的一个。 时钟分频单元根据第一分频时钟信号和所选择的第二分频时钟信号中的一个分频内部时钟信号。

公开(公告)号：US20140258607A1

公开(公告)日：2014-09-11

申请号：US14197883

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong SHIM ,  In-Dal SONG

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.

Abstract translation: 提供一种半导体存储器件及其操作方法。 半导体存储器件包括输入第一信号并输出​​第一延迟信号的缓冲器，输出第二信号的命令解码器，输入第一延迟信号和第二信号并产生掩模脉冲信号的掩码脉冲信号发生器， 以及输入第一延迟信号，第二信号和掩模脉冲信号并重新形成第一延迟信号或第二信号的信号整形器。

公开(公告)号：US20140254295A1

公开(公告)日：2014-09-11

申请号：US14198028

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong SHIM ,  In-Dal SONG ,  Young CHOI

IPC: G11C11/4063

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.

Abstract translation: 提供存储器件。 存储器件包括将第一位数据编程到多个存储器单元中; 识别处于第一状态并且其阈值电压等于或大于来自用第一位数据编程的存储器单元的第一电压的目标存储器单元; 接收要编程到存储器单元中的第二位数据; 通过对所述第二位数据执行第一处理来计算多个第三位数据; 响应于来自多个第三位数据的多个第三位数据中的每一个对存储器单元进行编程，选择将最大数目的目标存储器单元从第一状态改变到第二状态的第三位数据; 并将所选择的第三位数据编程到存储器单元中。

公开(公告)号：US20140266351A1

公开(公告)日：2014-09-18

申请号：US14212362

申请日：2014-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Sik NA ,  In-Dal SONG

IPC: H03L7/081

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03L7/0818 ,  H03L7/095

Abstract: A delay-locked loop circuit includes a phase detector and a coarse-lock detector. The phase detector receives a feedback clock and a first clock to generate first and second phase detecting signals, respectively. The coarse-lock detector generates a coarse-lock signal based on changes of phase of the first and second phase detecting signals.

Abstract translation: 延迟锁定环路电路包括相位检测器和粗略锁定检测器。 相位检测器接收反馈时钟和第一时钟以分别产生第一和第二相位检测信号。 粗锁检测器基于第一和第二相位检测信号的相位变化产生粗锁信号。

公开(公告)号：US20140181567A1

公开(公告)日：2014-06-26

申请号：US14097689

申请日：2013-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-Dae CHOI ,  In-Dal SONG

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G11C5/144 ,  G11C5/148 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Exemplary embodiments disclose a command control circuit including a command decoder configured to generate an internal command signal using a chip select (CS) signal and a command signal, and a CS gating logic configured to provide the CS signal to the command decoder, wherein the CS gating logic is further configured to provide the CS signal to the command decoder in response to a clock enable (CKE) signal being at a first level, and block the CS signal from the command decoder in response to the CKE signal being at a second level.

Abstract translation: 示例性实施例公开了一种命令控制电路，其包括命令解码器，其被配置为使用片选（CS）信号和命令信号产生内部命令信号，以及CS门控逻辑，其被配置为向命令解码器提供CS信号，其中CS 门控逻辑还被配置为响应于处于第一电平的时钟使能（CKE）信号而将CS信号提供给命令解码器，并且响应于CKE信号处于第二电平来阻止来自命令解码器的CS信号 。