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    MEMORY DEVICE AND METHOD OF OPERATING THE SAME FOR LATENCY CONTROL
    1.
    发明申请
    MEMORY DEVICE AND METHOD OF OPERATING THE SAME FOR LATENCY CONTROL 审中-公开

    公开(公告)号：US20190147927A1

    公开(公告)日：2019-05-16

    申请号：US16105368

    申请日：2018-08-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Ho JEON ,  Han-Gi JUNG ,  Hun-Dae CHOI

    IPC: G11C7/22 ,  H03L7/081 ,  H03K21/02 ,  H03L7/08 ,  G11C29/50

    Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

    DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    3.
    发明公开
    DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230253971A1

    公开(公告)日：2023-08-10

    申请号：US17888199

    申请日：2022-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junsub YOON ,  Hun-Dae CHOI

    IPC: H03L7/081 ,  H03L7/083 ,  G11C7/22

    CPC classification number: H03L7/0818 ,  H03L7/083 ,  G11C7/225

    Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

    DIVIDED CLOCK GENERATION DEVICE AND DIVIDED CLOCK GENERATION METHOD
    5.
    发明申请
    DIVIDED CLOCK GENERATION DEVICE AND DIVIDED CLOCK GENERATION METHOD 有权
    分时钟产生装置和分时钟产生方法

    公开(公告)号：US20140253188A1

    公开(公告)日：2014-09-11

    申请号：US14193595

    申请日：2014-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hun-Dae CHOI ,  In-Dal SONG

    IPC: H03K21/00

    CPC classification number: H03K23/42 ,  H03K23/667

    Abstract: A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

    Abstract translation: 时钟生成装置包括触发器，时钟分割单元和时钟比较器。 触发器产生与内部时钟信号同步的芯片选择信号。 时钟分割单元基于第一分频时钟信号产生第二分频时钟信号。 时钟比较器基于芯片选择信号选择第二分频时钟信号中的一个。 时钟分频单元根据第一分频时钟信号和所选择的第二分频时钟信号中的一个分频内部时钟信号。

    CLOCK CORRECTION CIRCUIT AND MEMORY SYSTEM COMPRISING THE CLOCK CORRECTION CIRCUIT
    6.
    发明申请
    CLOCK CORRECTION CIRCUIT AND MEMORY SYSTEM COMPRISING THE CLOCK CORRECTION CIRCUIT 有权

    公开(公告)号：US20220165322A1

    公开(公告)日：2022-05-26

    申请号：US17380206

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hun-Dae CHOI ,  Ga Ram CHOI

    IPC: G11C11/4076

    Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided. The clock correction circuit comprises a delay-locked loop circuit configured to receive a first clock signal and generate a second clock signal obtained by delaying the first clock signal; a first duty cycle correction circuit configured to receive the second clock signal and generate a first correction clock signal obtained by correcting a duty cycle of the second clock signal; and a duty cycle detection circuit which includes a second duty cycle correction circuit and an error code generation circuit, wherein the error code generation circuit receives the first correction clock signal, and generates a first error code as to whether to correct the duty cycle of the second clock signal on the basis of the first correction clock signal, the second duty cycle correction circuit generates a second correction clock signal obtained by correcting the duty cycle of the first correction clock signal in response to the first error code, the error code generation circuit generates a second error code as to whether to correct the duty cycle of the second clock signal on the basis of the second correction clock signal, and the first duty cycle correction circuit receives the second error code, and generates a third correction clock signal obtained by correcting the duty cycle of the second clock signal in response to the second error code.

    DELAY-LOCKED LOOP CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND METHODS OF OPERATING DELAY-LOCKED LOOP CIRCUIT
    7.
    发明申请
    DELAY-LOCKED LOOP CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND METHODS OF OPERATING DELAY-LOCKED LOOP CIRCUIT 审中-公开

    公开(公告)号：US20200059226A1

    公开(公告)日：2020-02-20

    申请号：US16282870

    申请日：2019-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hun-Dae CHOI ,  Hwa-Pyong KIM

    IPC: H03K5/156 ,  G11C11/4076 ,  H03L7/081 ,  H03L7/089 ,  H03L7/08 ,  G11C11/4093

    Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

    OUTPUT BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    8.
    发明申请
    OUTPUT BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20180123593A1

    公开(公告)日：2018-05-03

    申请号：US15688532

    申请日：2017-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hun-Dae CHOI

    IPC: H03K19/0185 ,  G11C7/10 ,  G11C29/02

    CPC classification number: H03K19/018564 ,  G11C7/1051 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H03K3/012 ,  H03K17/16 ,  H03K19/018521 ,  H03K19/018571 ,  H03K19/018585 ,  H03K19/094

    Abstract: An output buffer circuit may include a pulse generator, a transmitter, and an emphasis controller. The pulse generator generates a pulse signal for determining an emphasis execution period. The transmitter may receive an input data and to have a first output resistance value, which is determined by the input data and a resistance calibration code, and to have a second output resistance value different from the first output resistance value, which is determined by the input data and an emphasis code different from the resistance calibration code for executing an emphasis operation during the emphasis execution period, based on the pulse signal. The emphasis controller provides the resistance calibration code or the emphasis code to the transmitter based on the pulse signal. The emphasis code may include a first code determined by the input data regardless of the resistance calibration code.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND SLEW RATE CALIBRATION METHOD THEREOF
    9.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND SLEW RATE CALIBRATION METHOD THEREOF 审中-公开

    公开(公告)号：US20180131374A1

    公开(公告)日：2018-05-10

    申请号：US15689855

    申请日：2017-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hun-Dae CHOI

    IPC: H03K19/00 ,  H03K3/011

    CPC classification number: H03K19/0005 ,  H03K3/011

    Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.

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