公开(公告)号：US20210028146A1

公开(公告)日：2021-01-28

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20210143116A1

公开(公告)日：2021-05-13

申请号：US17007223

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JISEOK HONG ,  HYUEKJAE LEE ,  JONGPA HONG ,  JIHWAN HWANG ,  TAEHUN KIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US20230253363A1

公开(公告)日：2023-08-10

申请号：US18133959

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/80 ,  H01L25/18 ,  H01L24/08 ,  H01L21/565 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240332255A1

公开(公告)日：2024-10-03

申请号：US18742838

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20220068863A1

公开(公告)日：2022-03-03

申请号：US17500079

申请日：2021-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： JISEOK HONG ,  HYUEKJAE LEE ,  JONGPA HONG ,  JIHWAN HWANG ,  TAEHUN KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non- conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1μm to 100 um, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non- conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US20210125955A1

公开(公告)日：2021-04-29

申请号：US16992895

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHWAN SUH ,  UN-BYOUNG KANG ,  TAEHUN KIM ,  HYUEKJAE LEE ,  JIHWAN HWANG ,  SANG CHEON PARK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.