公开(公告)号：US20210143116A1

公开(公告)日：2021-05-13

申请号：US17007223

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JISEOK HONG ,  HYUEKJAE LEE ,  JONGPA HONG ,  JIHWAN HWANG ,  TAEHUN KIM

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

公开(公告)号：US20230253363A1

公开(公告)日：2023-08-10

申请号：US18133959

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/80 ,  H01L25/18 ,  H01L24/08 ,  H01L21/565 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240234349A9

公开(公告)日：2024-07-11

申请号：US18234529

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.

公开(公告)号：US20210028146A1

公开(公告)日：2021-01-28

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240072003A1

公开(公告)日：2024-02-29

申请号：US18221465

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUEKJAE LEE ,  MINKI KIM ,  SEUNGDUK BAEK

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/09 ,  H01L25/105 ,  H01L2224/08148 ,  H01L2224/08238 ,  H01L2224/0903 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A semiconductor device includes a first chip and a second chip stacked on the first chip. The first chip includes a first substrate, a first upper pad on an upper surface of the first substrate, a first upper insulating layer surrounding a lower portion of the first upper pad and a sacrificial layer surrounding an upper portion of the first upper pad. The second chip includes a second substrate, a second upper pad on an upper surface of the second substrate and a second upper insulating layer surrounding the second upper pad, wherein a thickness of the second upper pad is less than a thickness of the first upper pad.

公开(公告)号：US20220028834A1

公开(公告)日：2022-01-27

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JINKYEONG SEOL ,  SANGHOON LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

公开(公告)号：US20160314996A1

公开(公告)日：2016-10-27

申请号：US15099926

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： IL HWAN KIM ,  Sang Hyun BAE ,  HYUEKJAE LEE ,  Taeje CHO ,  Kwang-chul CHOI

IPC: H01L21/67 ,  H01L21/687

CPC classification number: H01L21/67051 ,  B24B7/228

Abstract: The inventive concepts relate to a substrate treating apparatus and a method for treating a substrate using the same. The apparatus includes a spin chuck configured to support a substrate, a grinding head disposed over the spin chuck and configured to grind the substrate supported by the spin chuck, and a nozzle member including a jet nozzle configured to jet high-pressure water to the substrate supported by the spin chuck. The jet nozzle overlaps with the substrate to jet the high-pressure water to an edge of the substrate.

Abstract translation: 本发明的概念涉及基板处理装置和使用其的基板的处理方法。 该装置包括配置成支撑基板的旋转卡盘，设置在旋转卡盘上方并构造成研磨由旋转卡盘支撑的基板的研磨头，以及包括喷射喷嘴的喷嘴构件，该喷嘴构造成将高压水喷射到基板 由旋转卡盘支撑。 喷射喷嘴与基板重叠以将高压水喷射到基板的边缘。

公开(公告)号：US20240404970A1

公开(公告)日：2024-12-05

申请号：US18441578

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINKI KIM ,  RAEYOUNG KANG ,  JIHOON KIM ,  JINKYEONG SEOL ,  HYUEKJAE LEE

IPC: H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: A semiconductor package includes a first die having signal and dummy regions, and a second die on the first die. The first die includes first dummy patterns arranged in a first direction on the dummy region, second dummy patterns on the dummy region and between the first dummy patterns, a first dielectric layer on the first and second dummy patterns, and first pads extending through the first dielectric layer and coupled to the first dummy patterns. The second die includes second pads on the dummy region, and third pads on the dummy region. On an interface between the first and second dies, the first pads are in contact with the second pads. The first dielectric layer is between the second dummy patterns and the third pads. The first dummy patterns are connected to a ground circuit or power circuit of the first die.

公开(公告)号：US20240332255A1

公开(公告)日：2024-10-03

申请号：US18742838

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240136311A1

公开(公告)日：2024-04-25

申请号：US18234529

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.