公开(公告)号：US20180081584A1

公开(公告)日：2018-03-22

申请号：US15676651

申请日：2017-08-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： HEE HYUN NAM ,  Young Sik Kim ,  JIN WOO KIM ,  Young Jo Park ,  Jae Geun Park ,  YOUNG JIN CHO

IPC分类号： G06F3/06

CPC分类号： G06F3/0644 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0679

摘要： A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

公开(公告)号：US20180189206A1

公开(公告)日：2018-07-05

申请号：US15844165

申请日：2017-12-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JEONG HO LEE ,  SUNG ROH YOON ,  EUI YOUNG CHUNG ,  JIN WOO KIM ,  YOUNG JIN CHO ,  MYEONG JIN KIM ,  SEI JOON KIM ,  JEONG BIN KIM ,  HYEOK JUN CHOE

IPC分类号： G06F13/16 ,  G06F13/28

摘要： A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.

公开(公告)号：US20130243147A1

公开(公告)日：2013-09-19

申请号：US13770836

申请日：2013-02-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JIN WOO KIM ,  KYOUNG MIN KOH ,  KYUNG-MIN KIM ,  HEE SUNG CHAE

IPC分类号： H03M1/12

CPC分类号： H03M1/12 ,  H03M1/0863 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3765 ,  H04N5/378

摘要： An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n-1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n-1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

摘要翻译： 图像传感器包括多个计数器和一个计数器控制器。 多个计数器的每个计数器被配置为执行比较结果信号的计数并产生计数结果，比较结果信号是通过比较斜坡信号和多列列的像素信号而获得的。 计数器控制器被配置为分别产生并发送计数器时钟信号和（n-1）个延迟时钟信号给计数器，“n”是等于或大于2的自然数。 通过将计数器时钟信号延迟相应的偏移代码来获得（n-1）个延迟时钟信号的每个延迟时钟信号。