公开(公告)号：US20230068587A1

公开(公告)日：2023-03-02

申请号：US17853205

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yae Jung YOON ,  Eung Kyu KIM ,  Min Jun BAE ,  Kyoung Lim SUK ,  Seok Hyun LEE ,  Jae Gwon JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/053

Abstract: A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

公开(公告)号：US20220216068A1

公开(公告)日：2022-07-07

申请号：US17656695

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Seok Hyun LEE ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US20210066149A1

公开(公告)日：2021-03-04

申请号：US16866594

申请日：2020-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

公开(公告)号：US20210257223A1

公开(公告)日：2021-08-19

申请号：US17037003

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Seok Hyun LEE ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

公开(公告)号：US20210057317A1

公开(公告)日：2021-02-25

申请号：US16819318

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho PARK ,  Da Hye KIM ,  Jin-Woo PARK ,  Jae Gwon JANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.

公开(公告)号：US20240170413A1

公开(公告)日：2024-05-23

申请号：US18368376

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Gwon JANG ,  Jong Youn Kim ,  Seok Kyu Choi

IPC: H01L23/544 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/105 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L2223/54413 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Provided is a semiconductor package including a first wiring structure extending in a first direction and a second crossing the first direction, a first semiconductor chip stacked on the first wiring structure in a third direction different from the first direction and the second direction, a second wiring structure on the first semiconductor chip, the second wiring structure including an insulating layer and a first metal layer on the insulating layer, and a marking plate on the first metal layer, the marking plate including a first marking region and a second marking region different from the first marking region, wherein a shape of the first metal layer corresponding to the first marking region and a shape of the first metal layer corresponding to the second marking region are different from each other, and wherein a shape of an uneven structure in the first marking region and a shape of an uneven structure in the second marking region are different from each other.

公开(公告)号：US20220352050A1

公开(公告)日：2022-11-03

申请号：US17866866

申请日：2022-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Kyu KIM ,  Jung-Ho PARK ,  Jong Youn KIM ,  Yeon Ho JANG ,  Jae Gwon JANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/78 ,  H01L25/00 ,  H01L21/683

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

公开(公告)号：US20220262696A1

公开(公告)日：2022-08-18

申请号：US17735471

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho PARK ,  Jin-Woo PARK ,  Jae Gwon JANG ,  Gwang Jae JEON

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.